A control circuit and method for detecting a glitch signal on a bus are provided. The control circuit includes: input ends, respectively receiving a data signal and a clock signal from the bus; a counter, for calculating a time or a number of times in a low level period of the clock signal; a comparator, receiving an output of the time counted by the counter and a threshold value, and generating a comparison result by comparing the time and the threshold value; and an error detector, coupled to the comparator to receive the comparison result, and generating an error flag. When the comparison result indicates that there is a level change during the low level period of the clock signal, the error detector generates an error flag.

A signal correction circuit and a server are provided. The circuit comprises: a first signal processing component receiving an input signal and positive power supply voltages and negative power supply voltages, generating a first control voltage, and outputting a first voltage, the first voltage being zero within a first time period; a second signal processing component generating a second control voltage according to the first control voltage, performing energy storage charging according to the second control voltage, controlling an energy storage charging voltage according to the second control voltage, and outputting a second voltage, and the second voltage being zero in the second time period; and an output component performing superposition processing on the first voltage and the second voltage to obtain an output signal. In the disclosure, the ringback in an input signal can be eliminated, and in the circuit, a large amount of debugging and revision is not required.

A sigma delta (SD) pulse-width modulation (PWM) loop includes a loop filter implementing a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator configured to receive the loop filter signal and generate a sigma delta PWM signal based on the loop filter signal, wherein the first feedback signal is derived from the sigma delta PWM signal.

Dedicated circuitry may monitor a processor supply voltage and provide additional power on a temporary nano-second scale basis to the processor when the supply voltage drops below predetermined levels. This may be done without explicit knowledge of a commanded supply voltage level for the processor.

An on-board charger (OBC) for an electric vehicle includes a charge unit, a controller, and a control pilot (CP) wake-up circuit. The charge unit is operable for receiving energy from an EVSE for charging a traction battery of the vehicle. The controller while awake can control the charge unit to charge the battery with energy from the EVSE. The CP wake-up circuit receives a control pilot (CP) signal from the EVSE, detects for a change in a current state of the CP signal while the controller is asleep, and generates a wake-up signal for waking up the controller in response to the current state of the CP signal changing to a new state. The CP wake-up circuit includes first/second detector circuits usable for detecting for a change in the current state of the CP signal to a first/second new state.

A reference oscillator for a transmitter and/or a receiver of electromagnetic signals. The reference oscillator is suitable for generating a modified reference signal alternating ON times and OFF times with a predefined duty cycle from a signal supplied by a reference resonator. The reference oscillator also includes an adjustment circuit suitable for adjusting the duty cycle of the modified reference signal according to at least one adjustment parameter dependent on a rank of at least one harmonic component of the modified reference signal so as to minimize at least one harmonic component of the modified reference signal. A frequency synthesizer and a radio frequency signal receiver can include such a reference oscillator.

This disclosure provides systems, methods and apparatuses for processing analog signals with a wide dynamic range. In some implementations, the analog signal may be a current signal that is logarithmically scaled to decrease its dynamic range and converted to an output voltage using two or more diodes. A first diode may be used to scale a first range of the current signal and a second diode may be used to scale a second range of the current signal.

Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.

Clock distribution circuitry configured for duty cycle control, the circuitry comprising: a plurality of buffers connected in series along a clock path, each of the buffers having an input terminal and an output terminal, the input terminal being connected to the clock path via a corresponding AC coupling capacitor, and the clock, path configured to receive an input clock signal at its input node and output an output clock signal at its output node, the output clock signal having an output duty cycle; and control circuitry connected to apply a DC bias signal to the input terminal of each of the plurality of buffers, wherein the control circuitry is configured to: obtain a measurement signal indicative of the output duty cycle; and control the DC bias signals, based on a difference between the measurement signal and a reference signal, so as to control the output duty cycle.

A signal correction circuit and a server are provided. The circuit comprises: a first signal processing component receiving an input signal and positive power supply voltages and negative power supply voltages, generating a first control voltage, and outputting a first voltage, the first voltage being zero within a first time period; a second signal processing component generating a second control voltage according to the first control voltage, performing energy storage charging according to the second control voltage, controlling an energy storage charging voltage according to the second control voltage, and outputting a second voltage, and the second voltage being zero in the second time period; and an output component performing superposition processing on the first voltage and the second voltage to obtain an output signal.