Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage V.sub.GATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that V.sub.GATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust V.sub.GATE; connecting to the gate of the power FET allows V.sub.GATE to be directly set.

A reference oscillator for a transmitter and/or a receiver of electromagnetic signals. The reference oscillator is suitable for generating a modified reference signal alternating ON times and OFF times with a predefined duty cycle from a signal supplied by a reference resonator. The reference oscillator also includes an adjustment circuit suitable for adjusting the duty cycle of the modified reference signal according to at least one adjustment parameter dependent on a rank of at least one harmonic component of the modified reference signal so as to minimize at least one harmonic component of the modified reference signal. A frequency synthesizer and a radio frequency signal receiver can include such a reference oscillator.

A damping circuit having an input terminal and an output terminal is described. The damping circuit comprises a driver having an input and an output; an RC circuit coupled between the input terminal and the output; and a resistor coupled between the output and the output terminal, wherein the RC circuit delays passing a signal from the output terminal to the input terminal and a low impedance associated with the driver generally reduces ringing.

An encoder according to an embodiment of this disclosure includes a voltage generation circuit connected to a power supply through a diode and having a variable resistor, the voltage generation circuit outputting a voltage corresponding to a current flowing through the diode and a resistance value of the variable resistor, as a threshold value; a comparator for performing a comparison between an analog signal inputted from a detector for detecting rotation of a motor and the threshold value inputted from the voltage generation circuit, and outputting a comparison result as a comparator output; a resistance value variation circuit for varying the resistance value of the variable resistor; and a threshold value determination circuit for determining the threshold value based on a relationship between the resistance value and the comparator output.

To accurately detect the presence or absence of a signal. A signal detector includes an input-signal amplifying circuit, a reference-signal amplifying circuit, and a comparator. In the signal detector, the input-signal amplifying circuit amplifies an input signal with a predetermined gain. The reference-signal amplifying circuit amplifies a reference signal at a constant signal-level with a gain that substantially matches the predetermined gain. The comparator compares a signal level of the amplified input signal with a signal level of the amplified reference signal, and outputs the comparison result as a detection signal.

Dedicated circuitry may monitor a processor supply voltage and provide additional power on a temporary nano-second scale basis to the processor when the supply voltage drops below predetermined levels. This may be done without explicit knowledge of a commanded supply voltage level for the processor.

A method is described and in one embodiment includes detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode; placing the circuit in a second hysteresis mode subsequent to the detecting; and returning the receiver to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet. In certain embodiments, the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode. In some embodiments, a level of each of the first and second hysteresis modes is dynamically tunable.

Clock distribution circuitry configured for duty cycle control, the circuitry comprising: a plurality of buffers connected in series along a clock path, each of the buffers having an input terminal and an output terminal, the input terminal being connected to the clock path via a corresponding AC coupling capacitor, and the clock, path configured to receive an input clock signal at its input node and output an output clock signal at its output node, the output clock signal having an output duty cycle; and control circuitry connected to apply a DC bias signal to the input terminal of each of the plurality of buffers, wherein the control circuitry is configured to: obtain a measurement signal indicative of the output duty cycle; and control the DC bias signals, based on a difference between the measurement signal and a reference signal, so as to control the output duty cycle.

An example current limiting apparatus comprises a first transistor to carry a first current; a sense transistor coupled to the first transistor, the sense transistor to carry a sense current that is a function of the first current; a first amplifier coupled to the first transistor and the sense transistor, the amplifier to achieve a common voltage potential on terminals of the first and the sense transistors; a second amplifier coupled to the first amplifier and the sense transistor, the second amplifier to control the first and sense transistors based on the sense current; and a circuit coupled to the first and second amplifiers, the circuit to control an input to the second amplifier based on an input to the first amplifier such that a current limit of the first transistor remains below a programmed current limit of the first transistor.

An apparatus comprises a sensor circuit configured to detect activation of at least one circulator arranged to circulate liquid from a boiler through at least one circulation loop and back to the boiler. An analog up/down timer circuit has an input coupled to an output of the sensor circuit and generates a variable threshold signal that varies as a function of an activation time of the at least one circulator. A burner control circuit receives the variable threshold signal from the analog up/down timer circuit and generates an ignition control signal based at least in part on comparison of a temperature sensor signal of the boiler with the variable threshold signal. An ignition driver receives the ignition control signal from the burner control circuit and generates an ignition signal for a burner configured to burn fuel to heat the liquid in the boiler based at least in part on the ignition control signal.