A semiconductor integrated circuit includes a first signal transmission path and a second signal transmission path in parallel with each other, a first variable delay circuit provided on the first signal transmission path and configured to cause a first signal to be delayed by a first delay amount, a duty adjustment circuit provided on the first signal transmission path in series with the first variable delay circuit, and a second variable delay circuit provided on the second signal transmission path and configured to cause a second signal to be delayed by a second delay amount. The first delay amount is smaller than the second delay amount by a third delay amount corresponding to an amount of delay applied to the first signal by the duty adjustment circuit.

A voltage detection circuit for a charge pump is disclosed. The voltage detection circuit includes a sampling circuit and a latch circuit. The sampling circuit is configured to sample a supply voltage and provide the latch circuit with a sampled voltage. The latch circuit is configured to detect the sampled voltage and latch a result of the detection. And the latch circuit is connected to a voltage regulation circuit which is configured to regulate a charge-pump cascade structure in the charge pump based on the result of the detection so as to maintain an output voltage of the charge pump stable.

A passable latch circuit and variable delay chains built with one or more passable latch circuits are disclosed. The passable latch circuit has a dynamic latch including a first P-transistor, a first N-transistor, a second P-transistor, a second N-transistor and a clock input circuitry. The passable latch circuit further includes a control switch connected between the gates of the second P-transistor and the second N-transistor. The control switch has an on state and an off state, and the passable latch circuit is configured to have different delays by controlling the state of the control switch.

A Bluetooth Low-Energy (BLE) transmitter is presented for used in ultra-low-power radios in short range IoT applications. The power consumption of state-of-the-art BLE transmitter has been limited by the relatively power-hungry local oscillator due to the use of LC oscillators for superior phase noise performance. This disclosure addresses this issue by analyzing the phase noise limit of a BLE TX and proposes a ring oscillator-based solution for power and cost savings. The proposed transmitter features: 1) a wideband all-digital phase locked loop (ADPLL) featuring an f.sub.RF/4 RO, with an embedded 5-bit TDC; 2) a 4 frequency edge combiner to generate the 2.4 GHz signal; and 3) a switch-capacitor digital PA optimized for high efficiency at low transmit power levels. These not only help reduce the power consumption and improve phase noise performance, but also enhance the transmitter efficiency for short range applications.

A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180 phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.

Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.

A voltage detection circuit for a charge pump is disclosed. The voltage detection circuit includes a sampling circuit and a latch circuit. The sampling circuit is configured to sample a supply voltage and provide the latch circuit with a sampled voltage. The latch circuit is configured to detect the sampled voltage and latch a result of the detection. And the latch circuit is connected to a voltage regulation circuit which is configured to regulate a charge-pump cascade structure in the charge pump based on the result of the detection so as to maintain an output voltage of the charge pump stable.

Various implementations described herein refer to a device having an integrated circuit with multiple tiers including a first tier and a second tier that are arranged vertically in a stacked configuration. The first tier may have first functional components, and the second tier may have second functional components. The device may have a three-dimensional (3D) connection within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier.

The present disclosure relates to a charge pump circuit with a six-phase clock. The charge pump circuit comprises a six-phase clock circuit and a gate boosting charge pump configured to receive a plurality of clock signals from the six-phase clock circuit. The six-phase clock circuit includes provides a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, and a sixth clock signal. The gate boosting charge pump is configured to enable a charge-sharing operation to share the stored amount of charges between a plurality of parasitic capacitors. The six-phase clock circuit is configured to provide a dead time between each of the first, second, third, fourth, fifth and sixth clock.