An oscillator has an oscillator, an integer phase detector, a random number generator, an edge selector, a fractional phase detector, an offset correction arithmetic unit, and a phase error generator. The oscillator generates an oscillation signal having an oscillation frequency in accordance with a phase error signal. The integer phase detector detects an integer phase of the oscillation signal. The random number generator generates a random number. The edge selector outputs a phase difference signal indicating a phase difference between a phase of a reference signal and a phase of the oscillation signal, or indicating a phase difference acquired by offsetting the phase difference. The fractional phase detector detects a fractional phase of the oscillation signal based on the phase difference signal. The offset correction arithmetic unit computes an offset correction value in accordance with the random number. The phase error generator generates the phase error signal.

An analog front end circuit of an optical pulse energy digitizer includes a multiphase clock circuit, a demultiplexer configured to demultiplex a current pulse stream into demultiplexed current pulse streams, and integrate-and-dump circuits coupled with the demultiplexer. Each ingrate and dump circuit is configured to convert one of the demultiplexed current pulse streams to provide a demultiplexed voltage pulse stream. The multiphase clock circuit includes latches having outputs coupled to a combination logic circuit. The combination logic circuit is configured to provide clock signals for the integrate-and-dump circuits.

Provided is a memory device including a delay circuit having gate insulation films with thicknesses different from each other. The memory device includes a delay circuit configured to input an input signal and output an output signal, and circuit blocks configured to control an operation of reading or writing memory cell data in response to the input signal or the output signal. One of transistors constituting a circuit block has a gate insulation film having such a thickness that an effect of negative biased temperature instability (NBTI) or positive biased temperature instability (PBTI) on the transistors is minimized. The delay circuit may be affected little by a shift in a threshold voltage that may be caused by NTBI or PBTI, and thus, achieve target delay time.

Technologies are generally described herein for bandwidth amplification using a pre-clock signal to latch data at a latch in an input register of a sender section while passing the data through a multiplexer of the sender section in a serial manner. In some configurations, pre-clocking the multiplexer can allow for parallel operations to occur within the sender section, thus hiding or reducing the effects of certain serialization delays associated with the multiplexer. Furthermore, the pre-clocking of the multiplexer, in some configurations, hides or reduces the register latch hold and setup delays. A method may create three levels of parallelization of latencies between a sender circuit, a serialization circuit, and a receiver circuit by overlapping them at same time.

The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over ()}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over ()}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over ()}n phase signal in a first mode. The controller is further configured to provide the mode input of each of 2{circumflex over ()}(n1) odd stages with a first steady state signal and the mode input of each of 2{circumflex over ()}(n1) even stages with a second steady state signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with the same periodic binary signal as in the first mode to cause either the 2{circumflex over ()}(n1) odd stages or the 2{circumflex over ()}(n1) even stages to collectively generate a 2{circumflex over ()}(n1) phase signal in a second mode.

Embodiments of a multi-stage clock generator architecture that generates multiple non-overlapping clock phase signals includes: a first stage clock generator configured to: divide an input clock signal into a number of clock signals, synchronize each clock signal to a transition edge of a synchronization signal to produce synchronized clock signals, wherein the synchronization signal is a delayed version of the input clock signal by at least an amount sufficient to ensure that each of the clock signals become stable in response to a transition edge of the input clock signal, and generate a number of clock phase signals based on the synchronized clock signals. The architecture also includes a later stage clock generator configured to: generate a set of mutually non-overlapping clock phase signals based on the input clock signal.

A circuit for generating at least two rectangular signals with adjustable phase shift, comprises a frequency divider circuit that receives a clock signal as input and provides a signal as output, at least two comparators that receive, respectively, a first threshold voltage and at least a second threshold voltage at one input, and a ramp signal, synchronized with the clock signal, at a second input, the at least two threshold voltages allowing the value of the phase shift between the at least two rectangular signals to be adjusted, and at least two D-type flip-flops that receive, respectively, the output signal from the first comparator and the output signal from the second comparator at their clock inputs, and the output signal from the frequency divider circuit at their D-input.

A circuit comprises a cycle-cycle detector, configured to receive a synthesized clock signal, and detect a cycle difference index signal between any two neighboring cycles of the synthesized clock signal, wherein the synthesized clock signal is combined by a plurality of phase shifted signals; a demultiplexer connected to the cycle-cycle detector, configured to convert the cycle difference index signal into a plurality of parallel data signals; and a first state machine, connected to both the demultiplexer and the cycle-cycle detector, configured to generate a tuning signal based on the parallel data signals, and feed the tuning signal back to the cycle-cycle detector; wherein the cycle-cycle detector is further configured to adjust delay time of the synthesized clock signal according to the tuning signal.

A first flipflop outputs a first signal synchronized with a first clock signal. In the first transistor, the first clock signal is input to a first terminal and the second signal is output from a second terminal. In the fourth transistor, a first signal is input to a first terminal and a second terminal is electrically connected to a gate of the first transistor. In the sixth transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the fourth transistor, and the gate of the sixth transistor is electrically connected to the first terminal.

The present invention relates to a combiner latch circuit for generation of one phase differential signal pair or two phase differential signal pairs. The combiner latch circuit comprises an input circuit configured to select a state of the output circuit from a group of: a fourth state comprising the differential output X=1, Y=0, a fifth state comprising the differential output X=0, Y=1. The input circuit is further configured to select the fourth state if the input A=0 and the input B=1 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fifth state, and select the fifth state if the input A=1 and the input B=0 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fourth state.