A semiconductor device configured by bonding a first and a second chip together, including: a first signal output circuit provided at both the first and the second chip and driven by a first drive power; a second signal output circuit provided at both the first and the second chip and driven by a second drive power; a first phase comparison circuit, provided at the first chip, that compares a phase of a first signal and a second signal; a second phase comparison circuit that is provided at the second chip, and that compares a phase of a third signal and a fourth signal; a third phase comparison circuit, provided at the first chip, that compares a phase of a fifth signal and a sixth signal; and a fourth phase comparison circuit, provided at the second chip, that compares a phase of a seventh signal and an eighth signal.

A clock generation circuit includes a control clock generation circuit and first and second clock synchronization circuits. The control clock generation circuit compares a reference voltage with first and second feedback clock signals to generate first and second control clock signals. The first clock synchronization circuit makes the first and second feedback clock signals transit in synchronization with the first and second control clock signals. The second clock synchronization circuit generates first and second phase clock signals in synchronization with the first feedback clock signal and the second feedback clock signal.

A clock generation circuit includes a control clock generation circuit and first and second clock synchronization circuits. The control clock generation circuit compares a reference voltage with first and second feedback clock signals to generate first and second control clock signals. The first clock synchronization circuit makes the first and second feedback clock signals transit in synchronization with the first and second control clock signals. The second clock synchronization circuit generates first and second phase clock signals in synchronization with the first feedback clock signal and the second feedback clock signal.

A circuit for generating at least two rectangular signals with adjustable phase shift, comprises a frequency divider circuit that receives a clock signal as input and provides a signal as output, at least two comparators that receive, respectively, a first threshold voltage and at least a second threshold voltage at one input, and a ramp signal, synchronized with the clock signal, at a second input, the at least two threshold voltages allowing the value of the phase shift between the at least two rectangular signals to be adjusted, and at least two D-type flip-flops that receive, respectively, the output signal from the first comparator and the output signal from the second comparator at their clock inputs, and the output signal from the frequency divider circuit at their D-input.

A circuit for generating at least two rectangular signals with adjustable phase shift, comprises a frequency divider circuit that receives a clock signal as input and provides a signal as output, at least two comparators that receive, respectively, a first threshold voltage and at least a second threshold voltage at one input, and a ramp signal, synchronized with the clock signal, at a second input, the at least two threshold voltages allowing the value of the phase shift between the at least two rectangular signals to be adjusted, and at least two D-type flip-flops that receive, respectively, the output signal from the first comparator and the output signal from the second comparator at their clock inputs, and the output signal from the frequency divider circuit at their D-input.