Embodiments of the present disclosure provide a clock signal transmission circuit, a driving method thereof, a gate driving circuit, and a display device. The clock signal transmission circuit includes an input circuit, a pull-up circuit, a reset circuit, a pull-down control circuit, a pull-down circuit, and a pull-up holding circuit. According to an embodiment of the present disclosure, the clock signal source can be disconnected from each shift register unit in the gate driving circuit before a screen is displayed, preventing malfunctions of the gate driving circuit caused by an undesired high voltage on the clock signal line.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to third transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

A microelectronic circuit comprises a plurality of logic units and register circuits arranged into a plurality of processing paths. At least one monitor circuit (404) is associated with a first register circuit (301), said monitor circuit (404) being configured to produce a timing event observation signal as a response to a change in a digital value at an input (D) of the first register circuit (301) that took place later than an allowable time limit defined by a triggering signal (CP) to said first register circuit (301). A first processing path goes through a first logic unit (501) to said first register circuit (301) and is a delay critical processing path due to an amount of delay that it is likely to generate. The microelectronic circuit comprises a controllable data event injection point (503) for controllably generating a change of a digital value propagating to said first logic unit (501) irrespective of what other data is processed on said first processing path. Said microelectronic circuit is configured to freeze a first digital value stored in said first register circuit (301) for a time during which the change generated through said controllable data event injection point (503) propagates to said first register circuit.

Embodiments of the present disclosure provide a clock signal transmission circuit, a driving method thereof, a gate driving circuit, and a display device. The clock signal transmission circuit includes an input circuit, a pull-up circuit, a reset circuit, a pull-down control circuit, a pull-down circuit, and a pull-up holding circuit. According to an embodiment of the present disclosure, the clock signal source can be disconnected from each shift register unit in the gate driving circuit before a screen is displayed, preventing malfunctions of the gate driving circuit caused by an undesired high voltage on the clock signal line.

An example embodiment disclosed herein enables at least one frequency divider chain of a multiphase divider circuit to ensure proper phase relations after multiple frequency divisions. Another example embodiment enables a unique reset sequence to maximize a timing margin for reset signals of the at least one frequency divider chain and, thus, maximizes a bandwidth of the multiphase divider circuit.

An organic light-emitting diode display may have an array of pixel circuits. Each pixel circuit may contain an organic light-emitting diode that emits light, a drive transistor that controls current flow through the diode, and additional transistors such as switching transistors for loading data into the pixel circuit and emission transistors for enabling and disabling current flow through the drive transistor and diode. Gate driver circuitry may produce emission control signals that control the emission transistors. Display driver circuitry may generate a start signal with a digitally controlled pulse width. The start signal may be applied to shift register circuitry in the gate driver circuitry. The pulse width of the start signal may be adjusted to adjust the luminance of the display.

A transistor with excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) is provided. The transistor includes an oxide semiconductor layer including a channel formation region, a first gate electrode, a second gate electrode, a source electrode, and a drain electrode. The oxide semiconductor layer is between the first gate electrode and the second gate electrode. The oxide semiconductor layer has a pair of side surfaces in contact with the source electrode and the drain electrode and includes a region surrounded by the first gate electrode and the second gate electrode without the source electrode and the drain electrode interposed therebetween.

The present technology relates to a signal processing apparatus and method capable of increasing a harmonic rejection ratio while suppressing an increase in power consumption.

In one aspect of the present technology, two local signals having a 1/3 duty ratio and phases mutually shifted by a 1/2 period are mixed with each signal of a differential signal, and a difference between results of the mixing of the two local signals is calculated. The present technology can be applied to, for example, a signal processing apparatus, a transmission apparatus, a reception apparatus, a communication apparatus, an electronic apparatus having a transmission function, a reception function, or a communication function, or a computer that controls those apparatuses.

A first flipflop outputs a first signal synchronized with a first clock signal. In the first transistor, the first clock signal is input to a first terminal and the second signal is output from a second terminal. In the fourth transistor, a first signal is input to a first terminal and a second terminal is electrically connected to a gate of the first transistor. In the sixth transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the fourth transistor, and the gate of the sixth transistor is electrically connected to the first terminal.

An integrated circuit device includes a clock gating circuit, which is configured to generate a first plurality of clocks in response to a first reference clock at a first frequency and a plurality of operation enable signals. A plurality of functional circuits are provided, which are responsive to respective ones of the first plurality of clocks. The plurality of functional circuits is configured to generate respective ones of the plurality of operation enable signals, with each of the plurality of operation enable signals having a first logic state that enables a respective clock within said clock gating circuit and a second logic state that disables the respective clock within said clock gating circuit.