A comparator circuit includes an input stage with a set of differential current paths and a pair of differential input transistors connected to a pair of input terminals. An output stage includes an output current path between a first and a second supply terminal, an output transistor connected in the output current path and having a control terminal coupled to the set of differential current paths, and a comparator output connected to the output current path. An auxiliary stage includes an auxiliary current path between the supply terminals, an auxiliary current source, a first auxiliary transistor connected in the auxiliary current path and having a control terminal connected to the control terminal of the output transistor, and a voltage follower with a second auxiliary transistor and a third auxiliary transistor. The second auxiliary transistor controls the voltage follower and the third auxiliary transistor couples the control terminal of the output transistor to at least one of the set of differential current paths.

The present invention provides a current source comprising a first bias current control element, the first bias current control element being configured to generate a first current if the control value is lower than a reference value and configured to generate a second current if the control value equal to or higher than the reference value. In addition or alternatively the bias current source comprises a second bias current control element, the second bias current control element being configured to generate a third current if the control value is lower than or equal to the reference value and configured to generate a fourth current if the control value is higher than the reference value. Furthermore, the present invention provides an integrated circuit and a method.

In certain aspects, a comparator includes an input stage and a regeneration stage. The input stage includes a first input circuit coupled to a first node and a second node, a first switching transistor configured to enable the first input circuit if a previous bit value is one, a second input circuit coupled to the first node and the second node, and a second switching transistor configured to enable the second input circuit if the previous bit value is zero. The regeneration stage includes a first inverter, a second inverter cross coupled with the first inverter, a first drive transistor coupled to the first inverter, wherein a gate of the first drive transistor is coupled to the second node, and a second drive transistor coupled to the second inverter, wherein a gate of the second drive transistor is coupled to the first node.

A differential comparator has a first input and a second input comprises: first and second transistors arranged as a differential pair connected to the first and second inputs respectively; and a constant current arrangement disposed between said differential pair and a first supply rail;
wherein a first path between the first transistor and the constant current arrangement has a different resistance to a second path between the second transistor and the constant current arrangement.

Also disclosed is a radio receiver employing such a differential comparator.

A comparator includes an input stage having a differential input and an output, wherein the voltage at the output is in response to the voltage at the input. The comparator further includes a current limiter for limiting the current flow through the input stage, wherein the current flow through the input stage is in response to the voltage at the input.

A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.

The present description concerns a comparator (1) of a first voltage (V+) and of a second voltage (V−), comprising first (100) and second (102) branches each comprising a same succession of alternated first (106) and second (108) gates in series between a node (104) and an output (1002; 1022) of the branch (100; 102), wherein: each branch starts with a first gate (106), each gate (106; 108) has a second node (114) receiving a bias voltage, the second node (114) of each first gate (106) of the first branch (100) and of each second gate (108) of the second branch (102) receives the first voltage (V+), the second node of the other gates receiving the second voltage (V−), and an order of arrival of the edges on the outputs (1002; 1022) of the branches determines a result of a comparison.

A kickback current is suppressed so as not to generate a deviation in a signal that outputs a comparison result.

A comparator includes a first input terminal and a second input terminal to which a first differential input signal pair is input, a third input terminal and a fourth input terminal to which a second differential input signal pair is input, a first comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a positive side and connecting the second input terminal to a negative side and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and connecting the fourth input terminal to a negative side, and a second comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a negative side and connecting the second input terminal to a positive side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and connecting the fourth input terminal to a negative side.

The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.

The present technology relates to a signal processing apparatus, a control method, an image pickup element, and an electronic appliance that achieve the suppression of an increase in electric power consumption. The signal processing apparatus may be configured to control an amount of electric current at a differential stage in a comparison unit that compares signal levels of a plurality of signals and reduce the amount of electric current for a period other than this comparison period. For example, the amount of electric current may be reduced by turning off part of a group of switches each capable of disconnecting a path of an electric current from an electric current source. In addition, for example, the amount of electric current may be reduced by causing a gate potential at the electric current source unit to decrease. The present technology can be applied to, for example, an image pickup element and an electronic appliance.