A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.

A method includes: selectively generating a first current by a first current generating circuit according to a first control signal; generating a second current by a second current generating circuit; and comparing a first input signal and a second input signal at a common node to generate an output signal according to the first current, the second current, and a second control signal. The second control signal and the first control signal are in-phase with each other.

A circuit for processing a logic input, including a first comparator capable of comparing the logic input with a first reference voltage and of providing a logic output at a first output logic level if the logic input is higher than the first reference voltage and otherwise at a second output logic level different from the first output logic level. The power supply of the first comparator and the first voltage reference are activated by the logic input.

An inverter based on a compound semiconductor uses a depletion mode transistor as the pull-up device, and a current source to bias the pull-up device. The current source is electrically coupled to a source terminal of the pull-up device. As a result, the current source continues to conduct current through the pull-up device, whether the inverter output is high or low, to ensure rapid response of the inverter.

A glitch detector includes a sensing circuit, a glitch-to-pulse generator and a comparing circuit. The sensing circuit generates a glitch voltage and at least one reference voltage based on a first power supply voltage. The glitch-to-pulse generator receives the first power supply voltage or the glitch voltage, and generates at least one pulse voltage including a pulse when the glitch occurs on the first power supply voltage. The comparing circuit generates at least one detection voltage by comparing the glitch voltage with the at least one reference voltage based on the pulse included in the at least one pulse voltage. The at least one detection voltage is activated when the glitch occurs on the first power supply voltage.

A circuit for providing back-up power includes a switching circuit configured to be coupled to a first power source and a second power source. The circuit includes a domain voltage level monitor circuit coupled with the first power source and the second power source and with output of the switching circuit. The circuit includes a dynamic level shifter circuit coupled with the first power source and the second power source and an output of the domain voltage level monitor. The circuit includes a double controlled latch circuit coupled with the first power source and the second power source and an output of the dynamic level shifter circuit. The double controlled latch circuit is configured to provide control signals to the switching circuit.

A comparator is disclosed, for comparing a first input voltage (e+) with a second input voltage (e−) and generating a corresponding output voltage (out). The comparator comprises: a first input terminal (e+) for receiving the first input voltage: a second input terminal (e−) for receiving the second input voltage; an output terminal (out) for outputting the output voltage; a first supply rail (VCC) for providing a first supply voltage; and a second supply rail (VDD) for providing a second supply voltage. The comparator further comprises: a follower stage comprising a first follower stage supply terminal coupled to the first supply rail, a second follower stage supply terminal coupled to the second supply rail, a follower stage input terminal coupled to the second input terminal, and a follower stage output terminal for providing a follower stage output voltage; and an inverter stage comprising a first inverter stage supply terminal coupled to the first supply rail, a second inverter stage supply terminal coupled to the follower stage output terminal, an inverter stage input terminal coupled to the first input terminal, and an inverter stage output terminal for providing an inverter stage output voltage and coupled to the output terminal.

A solid-state imaging device that is capable of improving an imaging characteristic by enhancing a dynamic range of an ADC is provided. A solid-state imaging device that includes a pixel array including a plurality of pixels outputting a pixel signal by photoelectric conversion, and an AD conversion processing unit that performs AD conversion with respect to the pixel signal, and in which the AD conversion processing unit includes a comparator having a first amplifying unit that includes a pair of first differential pairs constituted of P-type transistors and a pair of second differential pairs constituted of N-type transistors, and a second amplifying unit that amplifies an output of the first amplifying unit, and in which a P-type transistor and an N-type transistor are connected in series is provided.

An image sensing device includes first and anterior comparators and first and second posterior comparators. The first anterior comparator generates a first anterior comparison signal based on a first pixel signal and a ramp signal. The first posterior comparator performs a first comparison that compares the first anterior comparison signal with a first reference signal under a first comparison precondition and generates a first posterior comparison signal corresponding to a result of the first comparison. The second anterior comparator generates a second anterior comparison signal based on a second pixel signal and the ramp signal. The second posterior comparator performs a second comparison that compares the second anterior comparison signal with a second reference signal under a second comparison precondition different from the first comparison precondition. The second posterior comparator generates a second posterior comparison signal corresponding to a result of the second comparison.

A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.