A lighting device for frequency-modulated emission of a light-emitting diode (LED). The lighting device allows for higher operating frequencies and has an improved quality of the emitted light signal. Embodiments of the lighting device include an LED; a resonant driver circuit with a tuned circuit that is configured to drive the LED at an operating frequency that is based on parameters of the LED.

Boot-strapping systems and techniques for circuits are described. One or more solid-state switches of a switched regulation circuit may be implemented using core transistors and the boot-strapping systems, rather than I/O transistors.

This invention pertains to a source follower circuit suitable for receiving and buffering an input voltage and providing the buffered input voltage to a sampling capacitor via a sampling switch. The source follower circuit employs a slew enhancement circuit which enables the source follower to have fast settling for both high-to-low and low-to-high transitions.

An expansion control circuit includes a delay circuit coupled to a first expansion module and a switching circuit coupled to a second expansion module. The switching circuit includes a buffer and a switching module. The buffer is coupled to the first expansion module. The first expansion module outputs a first control signal upon being switched on and outputs a second control signal after a working time. The delay circuit outputs a disconnecting signal upon being switched on. The buffer is switched off upon receiving the disconnect signal. The delay circuit further outputs a connecting signal after a delay time after outputting the disconnecting signal. The buffer is switched on upon receiving the connect signal. The buffer further outputs the second control signal to the switching module upon being switched on. The switching module controls the second expansion module to be switched on v receiving the second control signal.

A power electronic device includes first and second electronic switches, each integrated on a package having a low parasitic inductance, a supply terminal and a ground terminal. The first conduction terminal of the first switch may be coupled with the supply terminal, and the second conduction terminal of the second electronic switch may be coupled with the ground terminal. The corresponding control terminals of the switches may be coupled to corresponding pilot drivers. The package may include first and second electric terminals, wherein the second conduction terminal of the first switch is coupled to the first electric terminal, and the first conduction terminal of the second switch is coupled to the second electric terminal. A first inductance may be interposed between the first electric terminal and the output terminal and/or a second inductance interposed between the second electric terminal and the output terminal.

An RF switch arrangement includes a shunt switch having a first RF terminal, a second RF terminal coupled to ground, a main control input, and an acceleration control input; a series switch having a first RF terminal coupled to the first RF terminal of the shunt switch, a second RF terminal, a main control input, and an acceleration control input; and a switching time acceleration circuit having a positive acceleration path input, a negative acceleration path input, and a first output coupled to the main control input of the series switch.

A circuit structured to drive an isolated high speed voltage metal-oxide-semiconductor field-effect transistor (MOSFET) switch, including a first MOSFET and a second MOSFET configured to operate as a switch, a capacitor, a charging component in parallel with the capacitor, a first switch in series with the charging component, and a second switch in parallel with the charging component and the capacitor. The stored voltage in the capacitor is sent to the gates of the first MOSFET and the second MOSFET when a second switch is open and a first switch is closed.

An expansion control circuit includes a delay circuit coupled to a first expansion module and a switching circuit coupled to a second expansion module. The switching circuit includes a buffer and a switching module. The buffer is coupled to the first expansion module. The first expansion module outputs a first control signal upon being switched on and outputs a second control signal after a working time. The delay circuit outputs a disconnecting signal upon being switched on. The buffer is switched off upon receiving the disconnect signal. The delay circuit further outputs a connecting signal after a delay time after outputting the disconnecting signal. The buffer is switched on upon receiving the connect signal. The buffer further outputs the second control signal to the switching module upon being switched on. The switching module controls the second expansion module to be switched on v receiving the second control signal.

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a trickle current state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a trickle current state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.