A 3-level T-type neutral point clamped (NPC) inverter/rectifier is disclosed in which neutral point clamping is dynamically enabled/disabled responsive to load, e.g. enabled at low load for operation in a first mode as a 3-level inverter/rectifier and disabled at high/peak load for operation in a second mode as a 2-level inverter/rectifier. When the neutral clamping leg is enabled only under low load and low current, middle switches S2 and S3 can be smaller, lower cost devices with a lower current rating. Si, SiC, GaN and hybrid implementations provide options to optimize efficiency for specific load ratios and applications. For reduced switching losses and enhanced performance of inverters based on Si-IGBT power switches, a hybrid implementation of the dual-mode T-type NPC inverter is proposed, wherein switches S1 and S4 comprise Si-IGBTs and switches S2 and S3 of the neutral clamping leg comprise GaN HEMTs. Applications include electric vehicle traction inverters.

A circuit for controlling an anode-gate thyristor includes a first transistor that couples a thyristor gate to a first terminal to receive a potential lower than a potential of a second terminal connected to the thyristor anode. A control terminal of the first transistor is driven by a control signal which is positive with respect to the potential of the first terminal.

A sensor may include: a first plurality of resistors; a first BJT having: a first base terminal, a collector terminal, and an emitter terminal, where the collector terminal is coupled to the first plurality of resistors; and a first amplifier having a first non-inverting input coupled to the collector terminal and an output terminal coupled to the base terminal. The sensor may include: a second plurality of resistors; a second BJT having: a base terminal, a collector terminal, and an emitter terminal, where the base terminal is coupled to the base terminal of the first BJT, where the collector terminal is coupled to the second plurality of resistors; and a second amplifier having an inverting input coupled to the collector terminal and an output terminal coupled to the emitter terminal, wherein the inverting input terminal of the first amplifier is coupled to a non-inverting input terminal of the second amplifier.

A temperature sensor is disclosed. In one embodiment, the temperature sensor takes form in an integrated circuit that includes a plurality of first diodes connected in series between a first node and another node, and a plurality of second diodes connected in series between a second node and the other node. The integrated circuit includes a sub circuit coupled to the first and second nodes. The sub circuit the circuit is configured to generate an output voltage that depends on first and second voltages at the first and second nodes, respectively. The integrated circuit includes a first current source for generating a constant first current, wherein the first current or substantially all of the first current passes through the plurality of first diodes. A second current source is also provided on the integrated circuit for generating a constant second current, wherein the second current or substantially all of the second current passes through the plurality of second diodes. The plurality of first and second diodes are arranged on the integrated circuit so that they operate at a substantially equal temperature T.

Communication circuit for bidirectional communication. A switching part is provided including a first BJT having a first base, a first collector, and a first emitter connected to an IO line. The first BJT is activated in response to an input data signal. A transmitter part is provided including a second BJT having a second base connected to the first collector, and a second collector connected to an output. A receiver part is provided comprising a third BJT having a third base connected to an input, and a third collector connected to the first base and to the IO line. A diode is provided in the IO line for impeding current associated with an input data signal and conducting a current associated with an output data signal.

A bridge leg circuit assembly comprising: a circuit board, a first active switch die, and a second active switch die. The circuit board having an insulating plate with a first and second side and a first and second conducting layer on the first and second sides of the insulating plate, respectively. The second conducting layer having a first and second conducting region that are insulated from each other. The first active switch die having an opposing first side, facing and coupled with the first conducting region, and an opposing second side, coupled with the second conducting region, which are embedded into the circuit board. The second active switch die having an opposing first side, coupled with the second conducting region, and an opposing second side, coupled with the first conducting layer, which are embedded into the circuit board.

A semiconductor module includes a high-side switching device and a low-side switching device that respectively form an upper arm and a lower arm, freewheeling diodes that are respectively connected to the switching devices in anti-parallel, and a high-side driver circuit and a low-side driver circuit that respectively switch the high-side switching device and the low-side switching device ON and OFF. In the upper arm, an anode electrode of the freewheeling diode and a reference voltage electrode of the high-side driver circuit are directly connected via a first wiring, and the anode electrode of the freewheeling diode is connected to a reference voltage electrode of the high-side switching device via a second wiring having an inductance.

A system including a source follower circuit is disclosed. The source follower circuit configured as a voltage buffer that includes a first common-drain transistor that passes an input signal at the gate to an output loading capacitor at the source, and a second common-drain transistor that is used as a bias current source. The source follower circuit includes a first resistor at the drain of the first transistor generating a first voltage that is fed back through a first path through the gate of the second transistor so as to produce additional current to help the output signal catch up with the input voltage. The source follower circuit further includes an inductive element and bias circuit, which along with the first resistor, increases bandwidth and reduced settling time.

Satellite controller circuitry includes a connection (i.e. coaxial or single wire with ground), with a control unit receiving a data message and generating a response message as output, and transmitter circuitry transmitting the response message. The transmitter circuitry has a first transistor having a first conduction terminal coupled to the connection, a second conduction terminal coupled to ground, and a control terminal coupled to receive output from the control unit, a second transistor having a first conduction terminal coupled to the connection, a second conduction terminal coupled to ground, and a control terminal coupled to receive the output from the control unit. The first and second transistors are configured such that a second current flowing through the first conduction terminal of the second transistor is in a non-unity ratioed relationship, or in a unity ratioed relationship, with a first current flowing through the first conduction terminal of the first transistor.

The present disclosure relates to a control circuit of a triac or thyristor having its driving reference terminal connected to a first reference node and coupled to a voltage rectifier comprising at least a semiconductor device connected between the first reference node and a second reference node of the control circuit comprising: a first bipolar transistor; and a driving circuit of the first transistor referenced to the second reference node.