A single-pole double-throw switch includes switching units which are set between a first port and a second port and between the first port and a third port, respectively, and are configured to perform complementarily. The each switching unit includes an antenna port, a circuit port, a transmission line configured to couple them, and a switching element connected between the transmission line and a ground. The switching element includes a parallel circuit including a transistor and an inductor connected in parallel, and a capacitor connected in series with the parallel circuit. The transmission line has a characteristic impedance different from a impedance seen inside the switching unit from the antenna port and a impedance seen inside the switching unit from the circuit port.

A driver circuit includes three sub-circuits. A first sub-circuit is configured to generate a drive current output by the driver circuit through an output node during first and second regions of operation and includes: a diode coupled to the output node and a first transistor, and a second transistor coupled to the first transistor and a current mirror. A second sub-circuit is configured to generate the drive current during the first and second and a third region of operation and includes: a third transistor coupled to the output node; and a fourth transistor. A third sub-circuit is configured to generate the drive current during the third region of operation and includes: a current source coupled to the current mirror and a buffer; and a fifth transistor coupled to the third transistor and the fourth transistor and configured to receive an output of the buffer.

A driver circuit includes three sub-circuits. A first sub-circuit is configured to generate a drive current output by the driver circuit through an output node during first and second regions of operation and includes: a diode coupled to the output node and a first transistor, and a second transistor coupled to the first transistor and a current mirror. A second sub-circuit is configured to generate the drive current during the first and second and a third region of operation and includes: a third transistor coupled to the output node; and a fourth transistor. A third sub-circuit is configured to generate the drive current during the third region of operation and includes: a current source coupled to the current mirror and a buffer; and a fifth transistor coupled to the third transistor and the fourth transistor and configured to receive an output of the buffer.

A gate driver circuit drives a switching transistor. A variable current source generates a reference current configured to switch between a first current amount and a second current amount smaller than the first current amount. A current distribution circuit is configured to switch between a source enabled state in which a source current proportional to the reference current is sourced to a gate node of the switching transistor and a disabled state in which the source current is made equal to zero. A first transistor fixes the gate node of the switching transistor to a high voltage in an on-state of the first transistor. A second transistor fixes the gate node of the switching transistor to a low voltage in an on-state of the second transistor.

The disclosure relates to a latch including a first inverter with a first pair of field effect transistors (FETs) configured with a first channel width to length ratio (W/L), and a second inverter with a second pair of FETs configured with a second W/L different than the first W/L. Another latch includes first and second inverters; a first negative feedback circuit including first and second FETs coupled between first and second voltage rails, the input of the first inverter coupled between the first and second FETs, and the first and second FETs including gates coupled to an output of the first inverter; and a second negative feedback circuit including third and fourth FETs coupled between the first and second voltage rails, the input of the second inverter coupled between the third and fourth FETs, and the third and fourth FETs including gates coupled to an output of the second inverter.

Systems, methods, and apparatuses are provided for a single or multi-dimmer system having improved reliable connectivity between a dimmer assembly and a switch or between two or more dimmer assemblies.

A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

In some examples, a device comprises a first driver coupled to a first node, the first node to couple to a first load external to the device. The device comprises a second driver coupled to a second node, the second node coupled to a second load internal to the device. The device comprises a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node. Sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively.

In some examples, a device comprises a first driver coupled to a first node, the first node to couple to a first load external to the device. The device comprises a second driver coupled to a second node, the second node coupled to a second load internal to the device. The device comprises a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node. Sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively.