A signal conditioning circuit to reduce detrimental effects of analog circuit elements. The techniques described herein provide a cascade of buffer circuits and signal processing circuitry to measure and cancel the distortion introduced by the buffer circuits. Thus, a buffer can be added to the signal path of an input signal without the detrimental effects, such as added distortion, that typically accompany the addition of buffers.

A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.

In accordance with an embodiment, a method of controlling a switch driver includes energizing a first inductor in a first direction with a first energy; transferring the first energy from the first inductor to a second inductor, wherein the second inductor is coupled between a second switch-driving terminal of the switch driver and a second internal node, and the second inductor is magnetically coupled to the first inductor; asserting a first turn-on signal at the second switch-driving terminal using the transferred first energy; energizing the first inductor in a second direction opposite the first direction with a second energy after asserting the first turn-on signal at the second switch-driving terminal; transferring the second energy from the first inductor to the second inductor; and asserting a first turn-off signal at the second switch-driving terminal using the transferred second energy.

A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

A radio frequency (RF) switch includes a switchable RF path including a plurality of transistors coupled in series; a gate bias network including a plurality of resistors, wherein the gate bias network is coupled to each of the plurality of transistors in the switchable RF path; and a bypass network including a first plurality of transistors coupled in parallel to each of the plurality of transistors in the switchable RF path and a second plurality of transistors coupled in parallel to each of the plurality of resistors in the gate bias network.

In an example, a system includes a first power stage including a first power field effect transistor (FET) and a first sense transistor coupled to the first power FET. The system also includes a second power stage including a second power FET and a second sense transistor coupled to the second power FET, where the second power stage is smaller than the first power stage. The system includes a first switch coupled to a gate and a drain of the first power FET and a second switch coupled to the first power stage and the second power stage. The system also includes a sense amplifier coupled to the second switch, where the first power stage, the second power stage, and the sense amplifier are coupled to a load terminal.

In one example, an apparatus comprises: a voltage sensing circuit having a voltage sensing terminal and a voltage sensing output, the voltage sensing circuit configured to generate a first voltage at the voltage sensing output representing a second voltage at the voltage sensing terminal; a control circuit having a control circuit input and a control circuit output, the control circuit input coupled to the voltage sensing output, the control circuit configured to: determine a state of a transistor based on the first voltage; and generate a driver signal at the control circuit output based on the state; and a driver circuit having a driver input and a switch control output, the driver input coupled to the control circuit output, the driver circuit configured to provide a current at the switch control output responsive to the driver signal.

Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.

A rectangular power module with a body having two short ends defining a length and two long sides defining a width having three parallel circuit paths crossing the short width distance from side to side using side positioned gate terminals and planar top positioned top power terminal positioned between MOSFETS in the circuit for even thermal positioning and reduced current path, inductance, and resistance and increased power density.

A high-voltage semiconductor switch is provided. The high-voltage semiconductor switch comprises one or more switch subcircuits, wherein each switch subcircuit may comprise one or more FET circuits and voltage-shifting transistor. The high-voltage semiconductor switch may be configured based on operational and environmental requirements, such as those of a quantum computing system, wherein the high-voltage switch may be located in a cryostat or vacuum chamber.