An aspect relates to an apparatus including a first and second power rails; a first set of power switch cells coupled to the first and second power rails, the first set of power switch cells being cascaded from an output to an input of a control circuit; and a second set of power switch cells coupled to the first and second power rails, the second set of power switch cells being coupled to one of a pair of cells of the first set, the first output, and the first input of the control circuit. Another aspect relates to a method including propagating a control signal via a first set of cascaded power switch cells to sequentially couple a first power rail to a second power rail; and propagating the control signal via a second set of power switch cells coupled between a pair of cells of the first set.

An active two-terminal inductor device with a controllable inducitance based on an inductance value input L_I. A processor system PRS executes an algorithm which controls a power converter PCV with controllable electric switches connected to the two external terminals A, B along with a fixed value inductor component L1. Based on sampling of at least a voltage or a current in connection with the inductor component L1, the algorithm controls the power converter PCV to provide a resulting inductance across the external terminals A, B which serves to match the inductance value input L_I.

A power supply circuit portion for supplying power comprises a first power rail, a second power rail, first and second output terminals, an energy storage device connected in parallel with the first and second output terminals; and first and second switching portions. The power supply circuit portion has a first mode in which power is supplied to the first and second output terminals by the first and second power rails, and a second mode in which the first switching portion is arranged such that power is not supplied to the first and second output terminals and the second switching portion is arranged to disconnect the energy storage device from the first power rail.

An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.

A power supply comprising a first-stage capacitor configured to provide energy to a second stage power converter. An energy transfer element coupled to the first-stage capacitor. A reservoir capacitor coupled to the energy transfer element. The reservoir capacitor is configured to receive charge from the energy transfer element. A power switch configured to control a transfer of energy from an input of the power supply to the first-stage capacitor. A controller coupled to the power switch, the controller configured to generate a hold-up signal in response to the input of the power supply falling below a threshold voltage. A charge circuit comprising a first switch and a second switch configured to be controlled by the hold-up signal. The first switch couples the reservoir capacitor to an input of the energy transfer element. The second switch is configured to uncouple the reservoir capacitor from receiving charge from the energy transfer element.

A fuse structure includes first and second transistors where each of the first and the second transistors has a source terminal, a drain terminal, and a gate terminal; a first source/drain contact disposed on the source terminal of the first transistor; a second source/drain contact disposed on the drain terminal of the second transistor; an insulator disposed laterally between the first and the second source/drain contacts; a source/drain contact via disposed on the first source/drain contact; and a program line connected to the source/drain contact via, wherein a width of the insulator is configured such that a programming potential applied across the source/drain contact via and the drain terminal of the second transistor causes the insulator to break down.

Systems and methods for routing communication among a plurality of devices are described. In an example, a controller can detect a communication initiated from a first device to a target device among a second device and a third device. The controller can identify the second device as the target device. The controller can, in response to identifying the second device as the target device, activate a direct communication path between the first device and the second device to allow the first device to communicate with the second device using direct communication mode. The controller can, in response to identifying the second device as the target device, activate redriver path between the first device and the third device to allow the first device to communicate with the third device using redriver mode.

A digital step attenuator (DSA) cell and related method are provided. The DSA cell includes a first branch comprising a first resistor connected, at a first side, to an input port and, at a second side, to an output port; a second resistor connected, at a first side, to the first resistor and, at a second side, to a first transistor and a third resistor connected, at a first side, to the first resistor and, at a second side, to a second transistor. Also included in the DSA cell is a second branch, in a parallel configuration with the first resistor, that includes a fourth resistor and a third transistor. Also included is a third branch, in a parallel configuration with the first resistor, that includes a fourth transistor. The first transistor, the second transistor, the third transistor, and the fourth transistor are configured to be operated independently.

This application relates to methods and apparatus for driving a transducer with switching drivers. A switching driver has first and second supply node for receiving supply voltages and includes an output bridge stage, a capacitor and a network of switches. The network of switches is operable in different switch states to provide different switching voltages to the output bridge stage. A controller is configured to control the switch state of the network of switches and a duty cycle of output switches of the output bridge stage based on an input signal to generate an output signal for driving the transducer.

An amplitude modulation circuit includes: first, second, and third input terminals; first and second output terminals; a current source; first and second transistors including a base electrically connected to the first and second input terminals, a collector electrically connected to the first and second output terminals, and an emitter electrically connected to a grounding terminal via the current source; first and second resistive elements electrically connected between the first and second output terminals and a power line; and a first MOS transistor including a drain connected to the first output terminal, a source connected to the second output terminal, and a gate connected to the third input terminal. The MOS transistor is configured to operate in a non-saturated region, and a resistance between the source and the drain of the MOS transistor is larger than resistances of the first and second resistive elements.