The present disclosure provides a high voltage device built from modular low voltage cells. Each low voltage cell includes a plurality of low voltage semiconductor devices and one or more low voltage passive components. Each cell can be a current-bidirectional two-quadrant switch or a four-quadrant switch. All the cells may be identical and controlled with a delay time in between. Therefore, the total on and off time of the high voltage device can be controlled to reduce the output equivalent dv/dt. The cell's voltage balancing can be achieved through a control algorithm disclosed herein.

A system may include an output power stage driver comprising a plurality of parallel-coupled field-effect transistors and a current sensor comprising a sense field-effect transistor matched to a matched field-effect transistor of the plurality of parallel-coupled field-effect transistors and gate-coupled and source-coupled to the matched field-effect transistor. The current sensor may be configured to measure a reference voltage across the sense field-effect transistor, measure a sense voltage across the matched field-effect transistor, and determine a current through the output power stage driver based on a comparison of the reference voltage to the sense voltage.

An arrayed switch circuit includes a substrate, signal conductive pads and signal expansion pins. The signal conductive pads are disposed on the substrate at intervals, and the signal conductive pads are arranged to form a signal conductive pad array. Each of the signal conductive pads has a row position and a column position in the signal conductive pad array. A row signal switch is provided between any two adjacent signal conductive pads corresponding to the same row position, and a column signal switch is provided between any two adjacent signal conductive pads corresponding to the same column position. The signal expansion pins are connected to the signal conductive pads located on at least one side of the signal conductive pad array through signal expansion switches respectively.

Provided are a determination device and a switch system capable of suppressing a power loss of a semiconductor switch. Determination device is used for semiconductor switch. Semiconductor switch includes junction field-effect transistor having gate and source corresponding to gate. Determination device includes resistor and determination circuit. Resistor has a first end and a second end. The first end of resistor is connected to gate. Determination circuit determines that overcurrent is flowing through semiconductor switch when there is a predetermined change in gate-source voltage of junction field-effect transistor in a range smaller than gate drive voltage provided between the second end of resistor and source.

The present disclosure relates to a bidirectional semiconductor circuit breaker including a primary circuit unit connected between a power supply and a load and in which a first semiconductor switch and a second semiconductor switch are arranged in series and a snubber circuit unit of which one end is connected to the front end of the first semiconductor switch and the other end is connected to the rear end of the second semiconductor switch, in parallel. The snubber circuit unit includes a first circuit line, a second circuit line, and a third circuit line of which one end and the other end are connected to the first circuit line and the second circuit line, respectively, and in which a first resistor and a second resistor are arranged in series, and provide a snubber circuit which is applicable to a bidirectional fault current and satisfies semiconductor protection and current restraining performance.

An electronic device is provided. The electronic device includes a tunable component and a first source follower circuit. The tunable component is electrically connected to a circuit node. The first source follower circuit is electrically connected to the circuit node. The first source follower circuit includes a first control terminal and a first terminal. The first control terminal is electrically connected to the first terminal.

A digital step attenuator (DSA) cell and related method are provided. The DSA cell includes a first branch comprising a first resistor connected, at a first side, to an input port and, at a second side, to an output port; a second resistor connected, at a first side, to the first resistor and, at a second side, to a first transistor and a third resistor connected, at a first side, to the first resistor and, at a second side, to a second transistor. Also included in the DSA cell is a second branch, in a parallel configuration with the first resistor, that includes a fourth resistor and a third transistor. Also included is a third branch, in a parallel configuration with the first resistor, that includes a fourth transistor. The first transistor, the second transistor, the third transistor, and the fourth transistor are configured to be operated independently.

A semiconductor device and a method for controlling body bias thereof capable of properly controlling body bias of a transistor even in a case where process variation occurs are provided. Operation speeds of ring oscillators ROSCn and ROSCp respectively change due to an influence of process variation at an NMOS transistor MN side and a PMOS transistor MP side. Speed/bias data represent a correspondence relationship between the operation speeds of the ring oscillators ROSCn and ROSCp and set values V1n and V1p of body biases VBN and VBP. A body bias controller receives speed values Sn and Sp measured for the ring oscillators ROSCn and ROSCp to which the body biases VBN and VBP based on default values are respectively applied, and obtains the set values V1n and V1p on the basis of the speed/bias data.

First and second switches are connected in series between first and second terminals. A third switch is provided between a first node between the first terminal and the first switch, and a first resistive-element. A fourth switch is provided between a second node between the first and second switches, and the reference power-source. A controller switches the first to fourth switches between conduction and non-conduction states. First, third, fifth, and seventh delay-circuits are provided between the first to fourth switches and the controller and delay first, second, third, fourth control signals for switching the first to fourth switches from a conduction state to a non-conduction state, respectively. Second, fourth, sixth, and eighth delay-circuits are provided between the first to fourth switches and the controller and delay the first, second, third, fourth control signals for switching the first to fourth switches to a non-conduction state to a conduction state, respectively.

An electric circuitry for signal transmission comprises a transmission gate having an input node to apply an input signal. The transmission gate includes a first transistor having an electric conductive channel of a first type of conductivity and a second transistor having an electric conductive channel of a second type of conductivity. The electric circuitry comprises a control circuit to control the signal transmission of the transmission gate. The control circuit is configured to generate a first and second control signal to control the conductivity of the first and second transistor in dependence on a voltage level of the input signal.