A semiconductor device according to embodiments includes a normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first element having a first end portion electrically connected to the first control electrode and a second end portion electrically connected to the first electrode, and the first element including a first capacitance component; and, a second element having a third end portion electrically connected to the first control electrode and the first end portion and a fourth end portion, and the second element including a second capacitance component, wherein, when a threshold voltage of the normally-off transistor is denoted by V.sub.th, a maximum rated gate voltage of the normally-off transistor is denoted by V.sub.g_max, a voltage of the fourth end portion is denoted by V.sub.g_on, the first capacitance component is denoted by C.sub.a, and the second capacitance component is denoted by C.sub.b, V.sub.th<(C.sub.b/(C.sub.a+C.sub.b))V.sub.g_on<V.sub.g_max.

A switching unit of an embodiment includes a first switching element of normally-on type, a second switching element of normally-off type having a non-reference potential side conductive terminal connected to a reference potential side conductive terminal of the first switching element, a series capacitor connected between a conduction control terminal of the first switching element and a conduction control terminal of the second switching element, and a diode having an anode connected to the conduction control terminal of the first switching element and a cathode connected to a common junction of the first switching element and the second switching element.

According to one aspect, embodiments herein provide a power switching circuit, comprising a first terminal, a second terminal, a third terminal, and a plurality of switching devices, each switching device having a first transistor having a first gate, a first source, and a first drain, a second transistor having a second gate, a second source, a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source, and a unipolar diode configured to prevent a transition voltage applied across the first gate and the first source from exceeding a degradation threshold of the first transistor during a transition period, wherein a first switching device of the plurality of switching devices is coupled between the first and third terminals and the and a second switching device of the plurality of switching devices is coupled between the second and third terminals.

A driving circuit is a circuit selectively outputting one of a staircase wave and a square wave from an output terminal, to drive a capacitive load, and includes a first power source supplying a constant voltage VH, a first FET connected between the output terminal and the first power source, a first transformer in which an output side coil is connected to a gate of the first FET, a first input terminal connected to an input side coil of the first transformer via a capacitive element, a second power source supplying a constant voltage VL, a second FET connected between the output terminal and the second power source, a second transformer in which an output side coil is connected to a gate of the second FET, and a second input terminal connected to an input side coil of the second transformer via a capacitive element.

A hybrid transistor circuit is disclosed for use in III-Nitride (III-N) semiconductor devices, comprising a Silicon (Si)-based Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Group III-Nitride (III-N)-based Field-Effect Transistor (FET), and a driver unit. A source terminal of the III-N-based FET is connected to a drain terminal of the Si-based MOSFET. The driver unit has at least one input terminal, and two output terminals connected to the gate terminals of the transistors respectively. The hybrid transistor circuit is turned on through the driver unit by switching on the Silicon-based MOSFET first before switching on the III-N-based FET, and is turned off through the driver unit by switching off the III-N-based FET before switching off the Silicon-based MOSFET. Also disclosed are integrated circuit packages and semiconductor structures for forming such hybrid transistor circuits. The resulting hybrid circuit provides power-efficient and robust use of III-Nitride semiconductor devices.

In a cascode switching device, avalanche breakdown of a control transistor and loss of soft switching or zero voltage switching in a high voltage normally-on depletion mode transistor having a negative switching threshold voltage and the corresponding losses are avoided by providing additional capacitance in parallel with a parallel connection of drain-source parasitic capacitance of the control transistor and gate-source parasitic capacitance of the high voltage, normally-on transistor to form a capacitive voltage divider with the drain-source parasitic capacitance of the high voltage, normally-on transistor such that the avalanche breakdown voltage of the control transistor cannot be reached. The increased capacitance also assures that the drain source parasitic capacitance of the high voltage, normally-on transistor is fully discharged before internal turn-on can occur.

According to one embodiment, a current detecting circuit includes: a normally-ON type first switching element that includes a drain, a source, and a gate; a normally-OFF type second switching element including a drain that is connected to the source of the first switching element, a source that is connected to the gate of the first switching element, and a gate; and a differential amplification circuit that outputs a voltage according to a voltage between the drain and the source of the second switching element.

In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.

A wide bandgap semiconductor device with an adjustable voltage level includes a wide bandgap semiconductor power unit and a level adjusting unit. The wide bandgap semiconductor power unit includes a source terminal, to which the level adjusting unit is electrically connected. The level adjusting unit provides a level shift voltage via the source terminal to adjust a driving voltage level of the wide bandgap semiconductor power unit. By adjusting the driving voltage level of the wide bandgap semiconductor power unit using the level adjusting unit, the wide bandgap semiconductor device may serve as a high-voltage enhancement-mode transistor to achieve reduced costs and an increased switching speed.

A rectifier circuit has one or more bridge circuits each with: a first leg with two diodes in series and an AC terminal at a midpoint between the two, a second leg with two semiconductor switches in parallel to the first, a third diode connected to a upper node of each leg, a fourth diode connected to a lower node of each leg, and a capacitor leg with two capacitors in series between the third and fourth diode. A midpoint between the capacitors is connected to a midpoint between the semiconductor switches. The first arrangement is two controllable semiconductor switches in series. A gate node of the second is connected to a first load terminal of the first switch and the first load terminal is connected to the lower node. The second semiconductor switch is a third controllable semiconductor switch with a gate node connected to the lower node.