The present disclosure describes a composite device including first field effect transistor (FET) device and second FET device. First FET device includes first drain, first source, first gate and shielding terminal. First FET device is made of wide-bandgap semiconductor material. Second FET device includes second drain, second source, and second gate. First and second FET devices are electrically connected in cascode configuration for providing a capacitive path between drain and gate terminals of composite device such that current flowing through gate terminal controls slew rate of drain voltage appearing at drain terminal. Cascode configuration includes an electrical connection of first drain to drain terminal, an electrical connection of first source to second drain, an electrical connection of second gate to first gate and gate terminal, an electrical connection of shielding terminal to second source, and an electrical connection of second source to source terminal of composite device.

An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

An auxiliary circuit for outputting a supplying voltage or a detection signal includes a normally-on device and a signal processing circuit. A drain terminal of the normally-on switching device is coupled to a first terminal, a gate terminal of the normally-on switching device is coupled to a second terminal. An input voltage between the first terminal and the second terminal switches between two different levels. The signal processing circuit is configured to output the supplying voltage or the detection signal according to a voltage at a source terminal of the normally-on switching device.

In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.

A semiconductor module includes: a semiconductor substrate; a switching element having a first electrode, a second electrode, and a gate electrode, and the switching element configured to perform turning on/off between the first electrode and the second electrode in response to applying of a predetermined gate voltage to the gate electrode; a control circuit part configured to control the gate voltage; and a current detection element configured to detect a current which flows between the first electrode and the second electrode of the switching element, wherein the switching element, the control circuit part, and the current detection element are mounted on the semiconductor substrate, and the current detection element is formed of a Rogowski coil.

In one embodiment, an RF power amplifier includes a first transistor and a second transistor in parallel, wherein a gate of the first transistor and a gate of the second transistor are configured to be driven by an RF source. A third transistor comprising a drain is operably coupled to both a source of the first transistor and a source of the second transistor. A control circuit is operably coupled to a gate of the third transistor and configured to alter a gate-to-source voltage of the third transistor, thereby altering a drain current of each of the first transistor and the second transistor, thereby altering an output power of the RF power amplifier.

Transformer-driven power switch devices are provided for switching high currents. These devices include power switches, such as Gallium Nitride (GaN) transistors. Transformers are used to transfer both control timing and power for controlling the power switches. These transformers may be coreless, such that they may be integrated within a silicon die. Rectifiers, pulldown control circuitry, and related are preferably integrated in the same die as a power switch, e.g., in a GaN die, such that a transformer-driven switch device is entirely comprised on a silicon die and a GaN die, and does not necessarily require a (large) cored transformer, auxiliary power supplies, or level shifting circuitry.

The present disclosure concerns a current limiting circuit for a power converter, which may be used to limit charge and discharge currents for electrical power storage units. In an example embodiment, a current limiting circuit comprises: first and second field effect transistors, each having source, gate and drain connections, wherein the source connection of the first transistor is connected to the gate connection of the second transistor and the source connection of the second transistor is connected to the gate connection of the first transistor; and a resistor connected between the source connections of the first and second transistors, wherein drain connections of the first and second transistors are connectable between a DC electrical power supply and an electrical load for limiting a maximum current flowing between the electrical power supply and the electrical load.

In one embodiment, an impedance matching network includes an electronically variable reactance element (EVRE) comprising discrete reactance elements and corresponding switches. The switches are configured to switch in and out the discrete reactance elements to alter a total reactance provided by the EVRE. A monitoring circuit is operably coupled to the EVRE. For each discrete reactance element, the monitoring circuit monitors a value related to the discrete reactance element or its corresponding switch. Upon determining the monitored value exceeds a predetermined amount, the monitoring circuit the discrete reactance element of the EVRE from switching in or out.

An auxiliary circuit for outputting a supplying voltage or a detection signal includes a normally-on device and a signal processing circuit. A drain terminal of the normally-on switching device is coupled to a first terminal, a gate terminal of the normally-on switching device is coupled to a second terminal. An input voltage between the first terminal and the second terminal switches between two different levels. The signal processing circuit is configured to output the supplying voltage or the detection signal according to a voltage at a source terminal of the normally-on switching device.