A semiconductor device includes a semiconductor body having an active region and a substrate region that is disposed beneath the active region, and a bidirectional switch formed in the semiconductor body. The bidirectional switch includes first and second gate structures that are each configured to control a conductive state of an electrically conductive channel that is disposed in the active region, and first and second input-output terminals that are each in ohmic contact with the electrically conductive channel. A passive substrate voltage discharge circuit in parallel with the bidirectional switch is configured to discharge a voltage of the substrate region in both directions of the bidirectional switch. The passive substrate voltage discharge circuit includes first and second normally-on switches connected in anti-series between the first and second input-output terminals in a common source configuration with the substrate region as a midpoint.

In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an inverter circuit. The first circuit has a function of generating an inverted signal of a signal input to an input terminal of the first circuit and outputting the inverted signal to an output terminal of the first circuit. The driver unit includes a p-channel first transistor and an n-channel second transistor having a back gate. The correction unit has a function of correcting the threshold voltage of one or both of the first transistor and the second transistor. The holding unit has a function of holding the potential of the back gate of the second transistor. The output terminal of the first circuit is electrically connected to an input terminal of the inverter circuit. The time from the input of a signal to the input terminal of the first circuit to the output of a signal from an output terminal of the inverter circuit depends on the potential of the back gate of the second transistor.

An analog switch includes a first field effect transistor (FET) which has a first terminal coupled to an input voltage terminal, a second terminal coupled to a common source, and a control terminal coupled to a common gate. The switch includes a second FET which has a first terminal coupled to an output voltage terminal, a second terminal coupled to the common source, and a control terminal coupled to the common gate. The switch includes a switched current source which has an input coupled to a high voltage supply terminal and an output coupled to the common gate. The switch includes a clamp circuit which has a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal coupled to the low voltage supply terminal.

A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.

In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an inverter circuit. The first circuit has a function of generating an inverted signal of a signal input to an input terminal of the first circuit and outputting the inverted signal to an output terminal of the first circuit. The driver unit includes a p-channel first transistor and an n-channel second transistor having a back gate. The correction unit has a function of correcting the threshold voltage of one or both of the first transistor and the second transistor. The holding unit has a function of holding the potential of the back gate of the second transistor. The output terminal of the first circuit is electrically connected to an input terminal of the inverter circuit. The time from the input of a signal to the input terminal of the first circuit to the output of a signal from an output terminal of the inverter circuit depends on the potential of the back gate of the second transistor.

The present disclosure provides a method and a device for simulation of a CMOS radio frequency switch and a communication terminal. The method includes: receiving a first value; obtaining a current value of a first function based on the first value, when the CMOS radio frequency switch is in an on-state, the value of the first function is a first function value, and when the CMOS radio frequency switch is in an off-state, the value of the first function is a second function value; receiving a second value; receiving a third value; outputting an off-state capacitance value of the CMOS radio frequency switch based on the second value and the third value; and outputting an on-state resistance value of the CMOS radio frequency switch based on the second value, the third value and the current value of the first function.

The present disclosure provides a method and a device for simulation of a CMOS radio frequency switch and a communication terminal. The method includes: receiving a first value; obtaining a current value of a first function based on the first value, when the CMOS radio frequency switch is in an on-state, the value of the first function is a first function value, and when the CMOS radio frequency switch is in an off-state, the value of the first function is a second function value; receiving a second value; receiving a third value; outputting an off-state capacitance value of the CMOS radio frequency switch based on the second value and the third value; and outputting an on-state resistance value of the CMOS radio frequency switch based on the second value, the third value and the current value of the first function.

Disclosed herein are quantum dot devices with patterned gates, as well as related computing devices and methods. For example, a quantum dot device may include gates disposed on a quantum well stack. In some embodiments, the gates may include a first gate with a first length; two second gates with second lengths arranged such that the first gate is disposed between the second gates; and two third gates with third lengths arranged such that the second gates are disposed between the third gates; and the first, second, and third lengths may all be different. In some embodiments, the gates may include a first set of gates alternatingly arranged with a second set of gates, spacers may be disposed between gates of the first set and gates of the second set, and gates in the first or second set may include a gate dielectric having a U-shaped cross-section.

In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an inverter circuit. The first circuit has a function of generating an inverted signal of a signal input to an input terminal of the first circuit and outputting the inverted signal to an output terminal of the first circuit. The driver unit includes a p-channel first transistor and an n-channel second transistor having a back gate. The correction unit has a function of correcting the threshold voltage of one or both of the first transistor and the second transistor. The holding unit has a function of holding the potential of the back gate of the second transistor. The output terminal of the first circuit is electrically connected to an input terminal of the inverter circuit. The time from the input of a signal to the input terminal of the first circuit to the output of a signal from an output terminal of the inverter circuit depends on the potential of the back gate of the second transistor.

A radio frequency switch is disclosed. The RF switch uses a combination of transistor technology and a topology to create an RF switch that has a high isolation and a high voltage breakdown at frequencies including those above a gigahertz.