An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.

An apparatus comprises an energy transfer device configured to supply power from a primary side of an isolation barrier through the isolation barrier to a secondary side of the of the isolation barrier for driving a gate of a switch for controlling output of the switch at the secondary side. The apparatus comprises a monitoring component. The monitoring component is configured to monitor an operating state of the switch. The monitoring component is configured to evaluate the operating state to determine whether a fault has occurred, perform a countermeasure, and/or provide a signal of the fault.

An apparatus comprises an energy transfer device configured to supply power from a primary side of an isolation barrier through the isolation barrier to a secondary side of the of the isolation barrier for driving a gate of a switch for controlling output of the switch at the secondary side. The apparatus comprises a monitoring component. The monitoring component is configured to monitor an operating state of the switch. The monitoring component is configured to evaluate the operating state to determine whether a fault has occurred, perform a countermeasure, and/or provide a signal of the fault.

A method for operating a gate driver system includes measuring a first parameter according to a first priority schedule synchronously to a first edge of a switching signal generated by a gate driver integrated circuit and having a variable duty cycle. The method includes after measuring the first parameter of the gate driver system and prior to a second edge of the switching signal, measuring at least a second parameter of the gate driver system according to a first round-robin schedule synchronously to the first edge of the switching signal.

A circuit arrangement comprises: a primary coil and a secondary coil, which are inductively coupled, but galvanically isolated from one another; a first voltage divider which is connected between a first terminal and a second terminal of the secondary coil and which has a center tap connected to a ground node; a second voltage divider, which is connected between the first terminal and the second terminal of the secondary coil; and an active circuit, which is connected to the first terminal and the second terminal of the secondary coil, a center tap of the second voltage divider and to the ground node. The active circuit is configured to provide a current path between the first terminal of the secondary coil and the ground node and between the second terminal of the secondary coil and the ground node depending on a voltage at the center tap of the second voltage divider.

A circuit arrangement comprises: a primary coil and a secondary coil, which are inductively coupled, but galvanically isolated from one another; a first voltage divider which is connected between a first terminal and a second terminal of the secondary coil and which has a center tap connected to a ground node; a second voltage divider, which is connected between the first terminal and the second terminal of the secondary coil; and an active circuit, which is connected to the first terminal and the second terminal of the secondary coil, a center tap of the second voltage divider and to the ground node. The active circuit is configured to provide a current path between the first terminal of the secondary coil and the ground node and between the second terminal of the secondary coil and the ground node depending on a voltage at the center tap of the second voltage divider.

According to one or more embodiments, a semiconductor device includes a mounting substrate and a semiconductor element on the mounting substrate. The mounting substrate has a first electrode pad and a second electrode pad. The semiconductor element has a supporting substrate, third and fourth electrode pads, first slits and second slits. The third and fourth electrode pads are provided on a first surface of the supporting substrate facing the mounting substrate. The first slits are provided both in the supporting substrate and in the third electrode pad. The second slits are provided both in the supporting substrate and in the fourth electrode pad. The semiconductor device further includes a first conductive bonding agent that connects the first electrode pad to the third electrode pad and a second conductive bonding agent that connects the second electrode pad to the fourth electrode pad.

According to one aspect of embodiments, a drive circuit of a normally-ON transistor includes: a normally-OFF transistor that includes a main current path connected in serial to a main current path of the normally-ON transistor; and a buffer circuit that supplies, to a gate of the normally-ON transistor, a control signal for controlling turning ON and OFF of the normally-ON transistor, whose high-voltage side and low-voltage side are biased by a bias voltage supplied from a power source unit.

According to one aspect of embodiments, a drive circuit of a normally-ON transistor includes: a normally-OFF transistor that includes a main current path connected in serial to a main current path of the normally-ON transistor; and a buffer circuit that supplies, to a gate of the normally-ON transistor, a control signal for controlling turning ON and OFF of the normally-ON transistor, whose high-voltage side and low-voltage side are biased by a bias voltage supplied from a power source unit.

The present description concerns a method of controlling at least one switch (TH), including: the reception of signals (S3-i) having between one another at least one phase shift representative of a desired state of said at least one switch; the obtaining, from said signals, of a value (Si) representative of the desired state; and the application of the representative value to said at least one switch.