Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.

A bootstrap circuit including a receiving circuit, a switched capacitor module and a booting circuit is provided. The receiving circuit receives an input signal to selectively output an output signal according to a control signal. The switched capacitor module is coupled to the input signal, and is arranged for generating the control signal according to the input signal. The booting circuit is coupled to the receiving circuit, and is arranged for applying an initial voltage when the control signal starts to enable the transistor, to increase a voltage level of the control signal.

A bootstrap circuit including a receiving circuit, a switched capacitor module and a booting circuit is provided. The receiving circuit receives an input signal to selectively output an output signal according to a control signal. The switched capacitor module is coupled to the input signal, and is arranged for generating the control signal according to the input signal. The booting circuit is coupled to the receiving circuit, and is arranged for applying an initial voltage when the control signal starts to enable the transistor, to increase a voltage level of the control signal.

The disclosure is directed at a CMOS-like logic gate including a set of thin-film transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; and wherein at least one of the subset of pull-down TFTs is connected to a first input.

An example continuous time linear equalizer (CTLE) includes a first inverter; a second inverter having an input to receive an input signal; a capacitor coupled between an input of the first inverter and the input of the second inverter; a resistor coupled between a common-mode voltage and the input of the first inverter; a third inverter having an output to provide an output signal; and a node comprising an output of the first inverter, an output of the second inverter, an input of the third inverter, and the output of the third inverter.

A level shifter includes a level switching circuit, an input circuit, and a first voltage drop circuit. The level switching circuit is configured to adjust a first voltage level of a first node and a second voltage level of a second node in response to a first input signal and a second input signal. The input circuit is configured to receive the first input signal and the second input signal. The first voltage drop circuit is coupled between the level switching circuit and the input circuit, and is configured to track a voltage level of a third node which is coupled to the first node, in order to be turned on according to the voltage level of the third node.

Exemplary embodiments of the present disclosure are directed to a bootstrapping module and logic circuits utilizing the bootstrapping module to compensate for a weak high condition. The bootstrapping module can be implemented using transistors have a single channel type that is the same as the channel type of transistors utilized in the logic circuits such that a truly unipolar circuit can be realized while addressing the weak high problem of such unipolar circuits.

A GaN logic circuit may include an input node receiving an input voltage, a first pull up transistor pulling up an output voltage in response to the input voltage, and a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied. The first depletion mode transistor may control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage. The logic device may further include a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.

A DC-to-DC converter is disclosed. The SMPS driver includes a highside switch having a first terminal, a second terminal and a gate. The first terminal is coupled to an input voltage terminal. The SMPS driver further includes a lowside switch having a first terminal, a second terminal and a gate. The first terminal of the lowside switch is coupled to the second terminal of the highside switch and the second terminal of the lowside switch is coupled to ground. A diode is coupled to the gate of the lowside switch on one side and to a capacitor on the other side. An integrated circuit (IC) is included to generate control signals for switching the highside switch and the lowside switch. The IC includes a highside supply pin, a highside gate control pin, a half bridge pin, a lowside gate control pin and a ground pin. The gate of the lowside switch is coupled to the lowside gate control pin, the highside supply pin is coupled to the diode and the capacitor is coupled to the half bridge pin.

A level shifter includes a level switching circuit, an input circuit, and a first voltage drop circuit. The level switching circuit is configured to adjust a first voltage level of a first node and a second voltage level of a second node in response to a first input signal and a second input signal. The input circuit is configured to receive the first input signal and the second input signal. The first voltage drop circuit is coupled between the level switching circuit and the input circuit, and is configured to track a voltage level of a third node which is coupled to the first node, in order to be turned on according to the voltage level of the third node.