A DC-to-DC converter is disclosed. The SMPS driver includes a highside switch having a first terminal, a second terminal and a gate. The first terminal is coupled to an input voltage terminal. The SMPS driver further includes a lowside switch having a first terminal, a second terminal and a gate. The first terminal of the lowside switch is coupled to the second terminal of the highside switch and the second terminal of the lowside switch is coupled to ground. A diode is coupled to the gate of the lowside switch on one side and to a capacitor on the other side. An integrated circuit (IC) is included to generate control signals for switching the highside switch and the lowside switch. The IC includes a highside supply pin, a highside gate control pin, a half bridge pin, a lowside gate control pin and a ground pin. The gate of the lowside switch is coupled to the lowside gate control pin, the highside supply pin is coupled to the diode and the capacitor is coupled to the half bridge pin.

According to some aspects, a circuit, such as an integrated circuit, comprises a bootstrap capacitor terminal, a bootstrap capacitor charging circuit coupled to the bootstrap capacitor terminal; and a bootstrap capacitor charging current limiting circuit coupled to the bootstrap capacitor charging circuit. According to some aspects, the circuit comprises a capacitor terminal, a capacitor charging transistor coupled to the capacitor terminal, a capacitor charging current sensing transistor coupled to the capacitor charging transistor, a current programming transistor coupled to the capacitor charging current sensing transistor; and a capacitor current limiting transistor coupled to the capacitor charging current sensing transistor, to the current programming transistor, and to the capacitor charging transistor. According to some aspects, an apparatus comprises a memory storing instructions to cause a processor to instantiate bootstrap capacitor charging current limiting circuit features.

A bootstrap circuit integrated to a voltage converter integrated circuit (IC) and a voltage converter IC for a switch mode voltage regulator. The bootstrap circuit is used to provide a bootstrap voltage signal for driving a high side switch of the voltage converter IC. The bootstrap circuit has a pre-charger and a bootstrap capacitor. The pre-charger provides a first bootstrap signal to pre-charge a control terminal of the high side switch, and the bootstrap capacitor provides a second bootstrap signal to enhance the charge of the control terminal of the high side switch.

In a switching circuit apparatus, first and second capacitors apply power supply voltages to first and second drive circuits. First and second diodes are connected such that currents flow from a DC voltage source to the first and second capacitors. A resistor and a Zener diode are connected in series between a terminal and a node, such that a reverse bias voltage is applied from the terminal to the Zener diode via the resistor. A third diode is connected such that a current flows to the first capacitor from a node (N2) between the resistor and the Zener diode.

Exemplary embodiments of the present disclosure are directed to a bootstrapping module and logic circuits utilizing the bootstrapping module to compensate for a weak high condition. The bootstrapping module can be implemented using transistors have a single channel type that is the same as the channel type of transistors utilized in the logic circuits such that a truly unipolar circuit can be realized while addressing the weak high problem of such unipolar circuits.

A voltage regulator includes a pass element, a buffer, and an error amplifier. The voltage regulator further includes a fast push-pull driver that has an inverter type amplification structure, is connected between a power output and a control input of the pass element, and reduces positive and negative peaks of the power output at a speed faster than a speed of a main feedback loop.

A pre-charge buffer for sampling input signals and generating a sampled output signal includes a coarse sampling circuit, a fine sampling circuit, and a sample and hold circuit. The coarse sampling circuit pre-samples the input signals during hold phases and for a first predetermined time interval during sample phases of the corresponding sample and hold cycles, and generates a first output signal. The fine sampling circuit samples the input signals during sample phases and generates a second output signal. The sample and hold circuit receives the first and second output signals, and generates a sampled output signal. The coarse sampling circuit provides the first output signal for a predefined time interval during the sample phases to reduce the effect of charge injection and charge sharing. The system uses bottom plate sampling to reduce charge injection caused by switches in the coarse sampling circuit.

It is an object to form a buffer circuit, an inverter circuit, or the like using only n-channel TFTs including an oxide semiconductor layer. A buffer circuit, an inverter circuit, or the like is formed by combination of a first transistor in which a source electrode and a drain electrode each overlap with a gate electrode and a second transistor in which a source electrode overlaps with a gate electrode and a drain electrode does not overlap with the gate electrode. Since the second transistor has such a structure, the capacitance C.sub.p can be small, and V.sub.A can be large even in the case where the potential difference VDDVSS is small.

The present invention relates to an inverter comprising: a first load transistor which has gate and drain electrodes connected to a power voltage (VDD) terminal; a second load transistor which has gate and drain electrodes connected to a source electrode of the first load transistor and has a source electrode connected to an output terminal; a driving transistor which has a drain electrode connected to the source electrode of the second load transistor to form the output terminal, has a gate electrode connected to an input (Vin) terminal, and has a source electrode connected to a ground (GND) terminal; and a control transistor which has a drain electrode connected to the source electrode of the first load transistor, has a gate electrode connected to the input (Vin) terminal, and has a source electrode connected to the ground (GND) terminal.

A data transmitter high side switch includes at least one output unit, an input logic unit, a reset circuit coupled to the input logic unit, a capacitor pump circuit coupled to the reset circuit and the input logic circuit, and operatively to the at least one output unit. The capacitor pump circuit includes at least one capacitor that is charged in a first direction during a time period when the input data signal is in a first logic level. During a subsequent time period, when the input data signal is in a second logic level, a reference voltage for the charge on the capacitor is changed to thereby provide an overdrive level turn-on voltage to a corresponding output transistor of the at least one output unit. The charge of the at least one capacitor can be adjustably selected to compensate for tolerance variations and/or ambient conditions to control output impedance.