The present invention provides an inverter and a bootstrap inverter with improved output characteristics. The inverter comprises a first and second load transistors, a driving transistor, and a control transistor. The control transistor, when turned on, effectively grounds the source of the first load transistor, ensuring a 0V output. The bootstrap inverter further includes a bootstrap transistor and a capacitor. This configuration solves the problems of output voltage being lower than VDD for logic 1 and not completely 0V for logic 0, achieving ideal output levels.

One or more examples relate to a complementary metal-oxide-semiconductor (CMOS) device. The CMOS device includes a CMOS pass gate circuit, a control circuit, and a bootstrap circuit. The CMOS pass gate circuit includes an n-channel transistor and a p-channel transistor. The control circuit may activate and deactivate the CMOS pass gate circuit. The bootstrap circuit may be electrically connected between the CMOS pass gate circuit and the control circuit. The bootstrap circuit may increase a first drive gain of the n-channel transistor and a second drive gain of the p-channel transistor.

A new inverting logic gate or a FET gate driver is disclosed. The logic gate mitigates the trade-off between power dissipation (or quiescent power) and slew rate of the typical RTL and DLL buffers by using an innovative circuit topology involving a pull-up bootstrapping transistor. The bootstrapping transistor may be an enhancement mode GaN field effect transistor (FET). This bootstrapping transistor may be driven by the complement of the input signal. Alternatively, the bootstrapping transistor may monitor the drain terminal of the pull-down transistor and conduct current accordingly. Other Boolean functions may also be achieved using this approach.

In some examples, an apparatus includes a switch circuit, a charge circuit, and a shutoff circuit. The switch circuit is configured to control passage of a data signal having a frequency of less than about 10 kilohertz (kHz) from an input terminal to an output terminal, the switch circuit having a control terminal. The charge circuit is coupled to a voltage supply and the switch circuit, wherein the charge circuit is configured to harvest a portion of current flowing through the switch circuit between the input terminal and the output terminal to maintain a charge at the control terminal greater than a programmed amount in a first state of operation and prevent charge from leaking from the control terminal. The shutoff circuit is coupled to the switch circuit and configured to discharge the charge at the control terminal in a second state of operation.

The present invention provides an inverter and a bootstrap inverter with improved output characteristics. The inverter comprises a first and second load transistors, a driving transistor, and a control transistor. The control transistor, when turned on, effectively grounds the source of the first load transistor, ensuring a 0V output. The bootstrap inverter further includes a bootstrap transistor and a capacitor. This configuration solves the problems of output voltage being lower than VDD for logic 1 and not completely 0V for logic 0, achieving ideal output levels.

An under voltage detection circuit compares a potential difference between a bootstrap line and an output line with a threshold voltage. A voltage line generates a voltage lower by a predetermined voltage than the bootstrap line. A current mirror circuit is connected to the bootstrap line. A first resistor and a MOS diode are connected in series between an input node of the current mirror circuit and the output line. A second resistor is connected between an output node of the current mirror circuit and the voltage line. A comparator compares a voltage drop across the second resistor with a threshold voltage.

In some examples, an apparatus includes a switch circuit, a charge circuit, and a shutoff circuit. The switch circuit is configured to control passage of a data signal having a frequency of less than about 10 kilohertz (kHz) from an input terminal to an output terminal, the switch circuit having a control terminal. The charge circuit is coupled to a voltage supply and the switch circuit, wherein the charge circuit is configured to harvest a portion of current flowing through the switch circuit between the input terminal and the output terminal to maintain a charge at the control terminal greater than a programmed amount in a first state of operation and prevent charge from leaking from the control terminal. The shutoff circuit is coupled to the switch circuit and configured to discharge the charge at the control terminal in a second state of operation.

A circuit device includes a pre-driver that drives a gate of a first N-type MOS transistor provided between a power supply node and a switch node, and a bootstrap circuit that generates a boot voltage of the pre-driver from a power supply voltage. A boot capacitor is provided between the switch node and a boot node that supplies a boot voltage to the pre-driver. The bootstrap circuit includes a P-type MOS transistor provided between the power supply node and the boot node, and a Schottky barrier diode. The Schottky barrier diode has an anode coupled to the power supply node and a cathode coupled to the boot node.