Disclosed herein is an apparatus that includes a first wiring layer including first and second conductive patterns extending in a second direction and coupled to source and drain regions, respectively, and a second wiring layer including third and fourth conductive patterns extending in the second direction and coupled to the first and second conductive patterns, respectively. The first conductive pattern has first and second sections arranged in the second direction, and the second conductive pattern has third and fourth sections arranged in the second direction. The first and fourth sections are arranged in a first direction, and the second and third sections are arranged in the first direction. The third conductive pattern covers the first section without covering the second section. The fourth conductive pattern covers the third section without covering the fourth section.

A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

A transmitter is disclosed with a pull-up feedback circuit and a feedback circuit. The transmitter includes an output driver for driving an output terminal.

Driver circuits to invert an input signal and to generate an output signal based on the inverted input signal are presented. The voltage level of the logical high value of the output signal is adjustable. The driver circuit has a high side switching element coupled between a supply terminal and the output terminal of the driver circuit. The driver circuit has a low side switching element coupled between the output terminal of the driver circuit and a reference potential. The driver circuit has a regulation transistor, wherein a controlled section of the regulation transistor is coupled in series with the high side switching element and the low side switching element between the supply terminal and the reference potential. The driver circuit has a feedback circuit to regulate the output voltage by generating a regulation voltage at a control terminal of the regulation transistor.

Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement is opposite the second series arrangement. The output of the first series arrangement is coupled to a first pull-up transistor and configured to cut off a pull-up of the first pull-up transistor to a first voltage. The output of the second series arrangement is coupled to a second pull-up transistor and configured to cut off a pull-up of the second pull-up transistor to the first voltage. The first series arrangement and the second series arrangement are coupled to a second voltage at different times. The series arrangements of transistors enable faster level shifting over conventional level shifters.

This document discusses, among other things, apparatus and methods for an edge rate driver for a power converter switch. In an example, the driver can include an input node configured to receive a pulse width modulated signal, a first switch configured to couple a control node of the power converter switch to a supply voltage during a first state, a second switch configured to couple the control node of the power converter switch to a reference voltage during a second state, and a first current source configured to supply charge current to the first switch when the power converter switch transitions from the second state to the first state, the charge current configured to charge a parasitic capacitance of the power converter switch.

Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

According to one embodiment, an antenna apparatus includes a plurality of amplifier circuits, a common drain control circuit, a gate control circuits, and an antenna controller. The common drain control circuit constitutes a control circuit common to the plurality of amplifier circuits, and controls a drain voltage of a field-effect transistor included in each of the amplifier circuits. The gate control circuits are provided for each amplifier circuit, and controls a gate voltage of the field-effect transistor. The antenna controller controls the common drain control circuit and the gate control circuits, and selectively operates the plurality of amplifier circuits by controlling an output of the gate voltage prior to the drain voltage.

An input-output (I/O) receiver includes a receiving terminal, a first N-type metal-oxide-semiconductor (NMOS) transistor, a reformation circuit, and a compensation unit. The receiving terminal is coupled with an external voltage signal. The first NMOS transistor has a source electrode coupled with the receiving terminal and a gate electrode coupled with a first power supply voltage. The reformation circuit is configured to reform a voltage signal transmitted from a drain electrode of the first NMOS transistor. The compensation unit includes a first PMOS transistor, a second PMOS transistor, and a second NMOS transistor. Moreover, the compensation unit is configured to provide a compensation voltage to a voltage signal at the drain electrode of the first NMOS transistor thereby a maximum level of the voltage signal at the drain electrode of the first NMOS transistor reaches the first power supply voltage.

A driving circuit includes: a primary driver configured to receive a first signal and generate a second signal based on the first signal, driving capability of the second signal being greater than that of the first signal; and an auxiliary driver connected to an output terminal of the primary driver and configured to receive the first signal and generate an auxiliary driving signal based on the first signal, the auxiliary driving signal being configured to shorten a rise time of the second signal.