A level translator translates signals between first and second voltage domains. An output buffer thereof includes a plurality of PFETs coupled in parallel between a second domain's output supply voltage and an output signal and a plurality of NFETs coupled in parallel between the output signal and the ground rail. Each gate of the plurality of PFETs is coupled to a respective first resistor; the first resistors are coupled in series and receive a first gate control signal. Each gate of the plurality of NFETs is coupled to a respective second resistor; the second resistors are coupled in series and receive a second gate control signal. A first booster NFET is coupled between the output supply voltage and the output signal and a second booster NFET is coupled between the output signal and the ground rail. The booster NFETs receive control signals that operate in the first voltage domain.

A level shifter includes a current mirror configured to receive an input signal in response to a first power voltage and generate an output signal by mirroring a current corresponding to a second power voltage based on a level of the input signal, a first adjusting circuit coupled to an output terminal of the current mirror and configured to adjust a voltage level of the output terminal of the current mirror in response to a bias voltage, and a second adjusting circuit coupled to a power voltage terminal which receives the second power voltage in parallel to the current mirror and configured to adjust the voltage level of the output terminal of the current mirror.

A level translator translates signals between first and second voltage domains. An output buffer thereof includes a plurality of PFETs coupled in parallel between a second domain's output supply voltage and an output signal and a plurality of NFETs coupled in parallel between the output signal and the ground rail. Each gate of the plurality of PFETs is coupled to a respective first resistor; the first resistors are coupled in series and receive a first gate control signal. Each gate of the plurality of NFETs is coupled to a respective second resistor; the second resistors are coupled in series and receive a second gate control signal. A first booster NFET is coupled between the output supply voltage and the output signal and a second booster NFET is coupled between the output signal and the ground rail. The booster NFETs receive control signals that operate in the first voltage domain.

A slew-limited output driver circuit facilitates finding a circuitry that allows a flexible setting of the slew-rate of an integrated circuit, with only a small footprint and latency, and which allows realizing different driver modes without additional components integrated protection against ESD. A short circuit will be solved by a slew-limited output driver circuit comprising a switchable current mirror providing an output current equal to an input current, wherein the current mirror is controlled by an additional switch, which is switched in response to control signals and/or an output current level of the output driver circuit, wherein adjustable operating modes of the slew-limited output driver circuit are realized by the control signals.

The disclosure relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT.

The present disclosure provides an off-chip driver (OCD) and an associated DRAM. The OCD operates in a power domain. The power domain works under a minimum system voltage and a maximum system voltage. The OCD is configured for providing a drive current to an output pad. The OCD includes a pull-push circuit. The pull-push circuit is coupled to the output pad. The pull-push circuit includes a current source circuit. The current source circuit includes a VCCS. The VCCS is configured to provide, in response to an operation voltage, an impedance with respect to the output pad, wherein the operation voltage ranges between the minimum system voltage and the maximum system voltage.

A full adder circuit includes a carry out generating circuit and a sum bit generating circuit. The carry out generating circuit is configured to generate a first output signal based on a first input signal, a second input signal and a third input signal. The sum bit generating circuit is configured to receive the first output signal and generate a second output signal based on the first input signal, the second input signal, the third input signal and the first output signal. The first output signal and the second output signal provide results of an arithmetic operation on the first input signal, the second input signal and the third input signal. The sum bit generating circuit includes a first pull-up network and a first pull-down network. There are at most two stacked transistors in at one or both of the first pull-up network and the first pull-down network.

A full adder circuit includes a carry out generating circuit and a sum bit generating circuit. The carry out generating circuit is configured to generate a first output signal based on a first input signal, a second input signal and a third input signal. The sum bit generating circuit is configured to receive the first output signal and generate a second output signal based on the first input signal, the second input signal, the third input signal and the first output signal. The first output signal and the second output signal provide results of an arithmetic operation on the first input signal, the second input signal and the third input signal. The sum bit generating circuit includes a first pull-up network and a first pull-down network. There are at most two stacked transistors in at one or both of the first pull-up network and the first pull-down network.

According to one embodiment, in a level shift circuit, a first PMOS transistor is electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, is electrically connected to a second node at a source, and is electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential is output. The first NMOS transistor is electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain. The second PMOS transistor is electrically connected to a node to be the second power-supply potential at a source, and is electrically connected to the second node at a drain. The potential adjusting circuit is electrically connected to at least the second node.

The disclosure relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT.