An integrated circuit includes a memory cell array coupled to a bitline and a first wordline and a negative-type metal-oxide-semiconductors (NMOS) pull-down structure coupled to the bitline and PMOS transistors. The positive-type metal-oxide-semiconductors (PMOS) transistors may be coupled to a second wordline, where a logic value carried on the second wordline is based on a logic value carried on the first wordline, and the PMOS transistors are structured to pre-charge respective drains of the NMOS pull-down structure to a high logic value based on a low logic value carried on the second wordline. The NMOS pull-down structure may be structured to discharge the bitline based on a high logic value carried on the second wordline.

A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

A static random access memory SRAM unit and a related apparatus are provided, to reduce power consumption of an SRAM when the SRAM memory is accessed. The SRAM unit is located in an SRAM memory, and the SRAM memory includes an SRAM storage array including a plurality of SRAM units. The SRAM unit includes: a storage circuit, connected to each of a write circuit and a read circuit, and configured to store data; the write circuit, configured to write data into the storage circuit; and the read circuit, configured to: after a read enabling signal is valid, enable data on a read bit line connected to the SRAM unit to be the data stored in the storage circuit.

A three-dimension (3D) memory device and an operation method thereof are provided. The 3D memory device includes: a memory array including a plurality of memory cells; a controller coupled to the memory array; and a match circuit coupled to memory array, wherein in data search and match, the controller selects from the memory cells a plurality of target memory cells sharing a same target global signal line, and the controller selects a plurality of target word lines sharing the target global signal line as a plurality of target search lines, wherein a search data sends to the target memory cells via the target search lines for data matching; the target global signal line is precharged; and outputting a match address based on whether a voltage on the target global signal line is pulled down or not.

A transmitter provides a duobinary signal corresponding to one of level 0, level 1, and level 2 based on first data and second data, and includes a pull-up driving circuit including a plurality of pull-up resistors selectively coupled between a first power source and a transmission node according to the first data and the second data; and a pull-down driving circuit including a plurality of pull-down resistors selectively coupled between the transmission node and a second power source, wherein at least one of the plurality of pull-up resistors is coupled between the first power source and the transmission node both when the first data is activated and when the second data is activated, or at least one of the plurality of pull-down resistors is coupled between the second power source and the transmission node both when the first data is activated and when the second data is activated.

A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.

An example system implementing a processing-in-memory pipeline includes: a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; a logic array coupled to the memory array, the logic array to implement configurable logic controlling the plurality of memory cells; and a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.

Compute-in-memory (CIM) bit cell array circuits include CIM bit cell circuits for multiply-accumulate operations. The CIM bit cell circuits include a memory bit cell circuit for storing a weight data in true and complement form. The CIM bit cell circuits include a true pass-gate circuit and a complement pass-gate circuit for generating a binary product of the weight data and an activation input on a product node. An RWL circuit couples the product node to a ground voltage for initialization. The CIM bit cell circuits also include a plurality of consecutive gates each coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit. Each of the CIM bit cell circuits in the CIM bit cell array circuit is disposed in an orientation of a CIM bit cell circuit layout including the RWL circuit.

A circuit includes a reference node having a reference voltage level, a first node that carries an input signal having a first voltage level or the reference voltage level, a second node that carries a power supply voltage, a voltage regulator including a source follower that outputs a gate signal having a fractional value of the input signal, a first control circuit that selects the higher of the power supply voltage or the gate signal as a first control signal, a second control circuit that selects the higher of the input signal or the first control signal as a second control signal, and first and second transistors coupled in series between the first node and the reference node and configured to receive the first and second control signals.

Provided is a method and an apparatus for optimizing memory power and provide a method and an apparatus for optimizing memory power by minimizing power consumed by pins of a memory by using an SBR pattern. The method of optimizing memory power using a PAM-4 (Pulse-Amplitude Modulation-4) method includes: setting a ratio and sizes of a pull-up transistor and a pull-down transistor included in a driver according to a smallest size of a plurality of eyes included in an eye diagram of a memory; and setting a reference voltage of a sampler and a phase interpolator (PI) digital code value included in the memory by using a signal bit response (SBR) pattern.