A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.

In some aspects of the present disclosure, an adder tree circuit is disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs) including: a first subgroup of FAs, wherein each FA of the first subgroup includes a first number of transistors; and a second subgroup of FAs, wherein each FA of the second subgroup includes a second number of transistors, the first number being greater than the second number; wherein each FA of the first subgroup receives a first input from a first one of the second subgroup of FAs and a second input from a second one of the second subgroup of FAs, and each FA provides a first output to a third one of the second subgroup of FAs and a second output to a fourth one of the second subgroup of FAs.

The present invention provides a clock buffer, wherein the clock buffer receives an input signal at a first node and generate an output signal at a second node. The clock buffer includes a P-type transistor, a first N-type transistor, a resistor, a transistor and a switch. A source electrode, a gate electrode and a drain electrode of the P-type transistor are coupled to a supply voltage, the first node, and the second node, respectively. A gate electrode, a drain electrode and a source electrode of the first N-type transistor are coupled to the first node, the second node and a third node, respectively. The resistor is coupled between the first node and the second node. The transistor is coupled between the first N-type transistor and a ground voltage. The switch is configured to selectively connect the third node to the ground voltage.

A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

A hybrid driver receives complementary high-speed input data signals and a pair of low-speed input data signals and selects one of the pairs of input data signals and drives output data signals on first and second output nodes based on the selected pair of input data signals. The hybrid driver includes first and second driver circuits coupled to the first and second output nodes, respectively. Each driver circuit includes first and second series-connected transistors coupled between a first supply voltage node and a reference voltage node, with an interconnection of the first and second series-connected transistors coupled to the corresponding first or second output node. Each first and second driver circuit includes a third transistor coupled in parallel with the corresponding first transistor. Each first and third transistor couples in parallel the corresponding output node to a second supply voltage node responsive to the corresponding low-speed input data signal.

A power supply switching circuit (100) and methodology are disclosed for connecting the greater of first and second power supplies (V.sub.SUP1, V.sub.SUP2) to an output voltage node (V.sub.OUT) with a comparator (102), active power supply switching circuit (103), gate driver circuit (106), and switching array (SW1-SW5) to generate control signals for a pair of PMOS power switches (MP1, MP2) by remapping first and second voltage supplies (V.sub.SUP1, V.sub.SUP2) to bias the n-wells of the PMOS power switches while simultaneously driving the gate terminals of the PMOS power switches with the gate driver circuit (106) only in response to a comparator activation signal by generating overlapping phase signals (PHI_1, PHI_2) which controls timing of first and second power supply selection signals so that a ground voltage is supplied as the first power supply selection signal only after the maximum bias voltage is supplied as the second power supply selection signal.

An output stage circuit includes a first operational amplifier, a second operational amplifier, a switch circuit, a clamp circuit and at least one pull-low transistor. The first operational amplifier is operated in a first voltage domain. The second operational amplifier is operated in a second voltage domain. The switch circuit is coupled to the first operational amplifier and the second operational amplifier. The clamp circuit is coupled between the switch circuit and a plurality of output terminals of the output stage circuit. The at least one pull-low transistor is coupled to the switch circuit.

A hybrid transmitter includes a current-mode driver, a voltage-mode driver and an auxiliary driver. The current-mode driver is configured to perform a current transmission. The voltage-mode driver is configured to perform a voltage transmission. The auxiliary driver, coupled to the current-mode driver and the voltage-mode driver, is configured to cooperate with the current-mode driver to enhance a driving capability of the current transmission and cooperate with the voltage-mode driver to enhance a driving capability of the voltage transmission.