An example apparatus includes a line driver and an interface circuit. The line driver has a plurality of source-series terminated (SST) driver segments including switching circuitry to selectively switch among at least three voltage-reference levels to drive an output node, common to each of the SST driver segments, in response to received digital signals by switching at a rate that is faster than a baud rate characterizing the received digital signals. The interface circuit drives a transmission link, in response to a drive signal at the output node, with an analog signal representing an oversampling of the received digital signals.

A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

There is provided a differential signal transmission circuit that includes a first output terminal, a second output terminal connected to the first output terminal via a load resistor, a high-side transistor formed of a p-channel MOSFET and connected between an application terminal of a power supply voltage and the first output terminal, a low-side transistor formed of an n-channel MOSFET and connected between an application terminal of a ground potential and the second output terminal, a high-side pre-driver configured to drive the high-side transistor, a low-side pre-driver configured to drive the low-side transistor, a first resistance part connected between an output end of the high-side pre-driver and a gate of the high-side transistor, and a second resistance part connected between an output end of the low-side pre-driver and a gate of the low-side transistor.

A hybrid driver receives complementary high-speed input data signals and a pair of low-speed input data signals and selects one of the pairs of input data signals and drives output data signals on first and second output nodes based on the selected pair of input data signals. The hybrid driver includes first and second driver circuits coupled to the first and second output nodes, respectively. Each driver circuit includes first and second series-connected transistors coupled between a first supply voltage node and a reference voltage node, with an interconnection of the first and second series-connected transistors coupled to the corresponding first or second output node. Each first and second driver circuit includes a third transistor coupled in parallel with the corresponding first transistor. Each first and third transistor couples in parallel the corresponding output node to a second supply voltage node responsive to the corresponding low-speed input data signal.

An example apparatus includes a line driver and an interface circuit. The line driver has a plurality of source-series terminated (SST) driver segments including switching circuitry to selectively switch among at least three voltage-reference levels to drive an output node, common to each of the SST driver segments, in response to received digital signals by switching at a rate that is faster than a baud rate characterizing the received digital signals. The interface circuit drives a transmission link, in response to a drive signal at the output node, with an analog signal representing an oversampling of the received digital signals.

A high-voltage level shifter circuit that is capable of level shifting a signal from a low-voltage rail to a high-voltage rail for effective gate driving of a top power switch, with a short propagation delay and a high common-mode transient immunity (CMTI). The high CMTI high-voltage level shifter circuit can include a differential input and isolation stage, a high dv/dt sensor and cancellation stage, at least one differential and common-mode gain stage, and an output buffer stage.

A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

A wide supply range digital level shifter circuit shifts between a variable desired output voltage ranging from a first voltage level and a second voltage level. The wide supply range digital level shifter circuit includes a latch circuit, a first bleeder circuit, and a second bleeder circuit. The latch circuit receives the first voltage level and the second voltage level, and includes first and second clocked differential switches. The first bleeder circuit is connected between the second voltage rail and the first differential switch and is configured to receive a first digital input voltage. The second bleeder circuit is connected between the second voltage rail and the second differential switch and is configured to receive a second digital input voltage. The first and second bleeder circuits isolate the first and second digital input voltages from the variable desired output voltage.

A capacitive-coupled level shifter includes a capacitive divider circuit having a first capacitive divider branch configured to couple a first input terminal to a first comparator terminal and a second capacitive divider branch configured to couple a second input terminal to a second comparator terminal. The first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of a modulated signal input to the capacitive divider circuit. A level shifter system which includes the capacitive-coupled level shifter is also described.

A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.