A multiphase serialization system for a voltage-mode transmitter includes a N-to-one stage driven by a N-phase input clock, a phase alignment unit driven by the N-phase input clock being operated to generated interpolated sampling clock signals by adjusting a plurality of reference clock signals provided to the phase alignment unit based on the N-phase input clock, and a preceding multiplexing stage driven by the interpolated sampling clock signals configured to receive incoming data streams and to output phase aligned data streams to the N-to-one stage.

Integrated circuit devices are provided. The devices may include a substrate including a first region, a second region and a boundary region between the first and second regions. The first and second regions may be spaced apart from each other in a first horizontal direction. The devices may also include a first latch on the first region, a second latch on the second region, and a conductive layer extending in the first horizontal direction and crossing over the boundary region. The first latch may include a first vertical field effect transistor (VFET), a second VFET, a third VFET, and a fourth VFET. The second latch may include a fifth VFET, a sixth VFET, a seventh VFET, and an eighth VFET. The first and seventh VFETs may be arranged along the first horizontal direction. Portions of the conductive layer may include gate electrodes of the first and seventh VFETs, respectively.

A circuit includes a clock generator configured to generate a first latching clock signal and a second latching clock signal. Responsive to a select signal, one of the first latching clock signal or the second latching clock signal has a clock signal frequency and the other of the first latching clock signal or the second latching clock signal has a predetermined logic value. A multiplexing latch circuit is configured to select either first data on a first data line or second data on a second data line based on the first latching clock signal and the second latching clock signal.

A integrated circuit includes a clock generator and a multiplexing latch circuit. The clock generator generates first and second latching clock signals in response to a select signal and a clock signal having a clock signal waveform, each of the first latching clock signal and the second latching clock signal having the clock signal waveform. The multiplexing latch circuit selects either first data on a first data line or second data on a second data line based on the first latching clock signal and the second latching clock signal, and stores and outputs the selected data.

A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.

Aspects of the present disclosure provide level-shifters and their use with switching converters. A level-shifter receives a binary signal on an input node and generates an output signal also representing the same logic level of the binary signal. The output signal represents logic levels in a first voltage range defined with respect to a first constant reference potential in a sequence of first phases of a clock signal and in a second voltage range defined with respect to a second constant reference potential in a sequence of second phases of the clock signal. The first constant reference potential is lower than the second constant reference potential. A controller block contained in the level-shifter receives the binary signal and transfers a changed logic level of the binary signal only in the first phase, but not in the second phase of the clock signal.

An architecture for high-performance flip-flops having minimal clock-activated transistors is disclosed. The flip-flops operating in a first voltage domain can receive an input signal from a second voltage domain. The flip-flops include a first latch electrically coupled to a second latch. The first latch includes a first output and a second output. The second latch further includes a first and a second keeper pull-up sub-circuit which electrically couples to the first and second output of the first latch. The clock-gating functionality of the first and second keeper pull-up sub-circuits is merged with the first latch to reduce the loading on the clock signal, and thus the operation of the flip-flop is contention-free and fully-static. An embodiment of the second latch includes only one clock-activated transistor for low-power application. Another embodiment includes two clock-activated transistors for high-speed application. The high-performance flip-flops have near-zero setup time and a two-stage propagation delay.

A semiconductor device having a first inverter electrically connected to a first node. A second inverter is electrically connected to a second node. A third clocked inverter is electrically connected to an output node of the first inverter. A fourth clocked inverter is electrically connected to an output node of the second inverter. A third inverter is electrically connected to an output node of a first clocked inverter and an output node of a second clocked inverter. A fourth inverter is electrically connected to an output node of the third clocked inverter and an output node of the fourth clocked inverter. A comparison circuit is electrically connected to an output node of the third inverter and an output node of the fourth inverter.

An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit; a data demodulation unit; and a data clock restoration unit.

Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.