An input buffer circuit may include a first switch that may couple a first voltage source to an output line based on an enable signal, such that the enable signal is configured to cause the input buffer circuit to operate. The input buffer circuit may also include a first set of switches that may couple the first voltage source to the output line based on the enable signal and an input signal, wherein the first switch and the first set of switches may couple the first voltage source to the output line in response to the input signal being greater than an input reference signal. The input buffer circuit may also include a switch that may couple a second voltage source to the output line in response to the input signal being less than the input reference signal.

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include clock circuitry having a first plurality of logic components arranged to receive a low voltage supply, a data input signal and a clock input signal and to provide a first plurality of intermediate signals and multiple intermediate clock signals. The integrated circuit may include level converter core circuitry having voltage biasing circuitry and voltage control circuitry arranged to receive a high voltage supply, the first plurality of intermediate signals and the multiple intermediate clock signals and to provide a second plurality of intermediate signals. The integrated circuit may include latch circuitry having a second plurality of logic components arranged to receive the high voltage supply, the low voltage supply and the second plurality of intermediate signals and to provide a data output signal.

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

A receiver includes the following: a signal receiving circuit, including a first MOS transistor and a second MOS transistor, where a gate of the first MOS transistor is configured to receive a reference signal and a gate of the second MOS transistor is configured to receive a data signal, and the signal receiving circuit is configured to output a comparison signal, the comparison signal being configured to represent a magnitude relationship between a voltage value of the reference signal and a voltage value of the data signal; and an adjusting circuit, including a third MOS transistor, where a source of the third MOS transistor is connected to a source of the first MOS transistor, a drain of the third MOS transistor is connected to a drain of the first MOS transistor, and a gate of the third MOS transistor is configured to receive an adjusting signal.

A level shifter includes a first power input terminal to which a first gate voltage may be applied; a second power input terminal to which a second gate voltage may be applied; a third power input terminal to which a third gate voltage may be applied; an output terminal; a first switch element configured to electrically connect the first power input terminal to the output terminal in response to a voltage of on-intervals of a first control signal; a second switch element configured to electrically connect the second power input terminal to the output terminal in response to a voltage of on-intervals of a second control signal; and a third switch element configured to electrically connect the third power input terminal to the output terminal in response to a voltage of on-intervals of a third control signal.

Provided are semiconductor circuits. A semiconductor circuit includes a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.