An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first controlled signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Devices and methods for finite impulse response (FIR) feed forward equalization (FFE) at a transmitter are provided. A voltage-mode driver circuit has a main driver and an equalization driver. The main driver drives the digital output signal based on a received digital input signal. The equalization function of the equalization driver is enabled or disabled for a short duration of time to provide at least one of FIR equalization and pre-emphasis to the digital output signal. Pre-emphasis is effected by enabling a low-resistance path of the equalization driver based on the digital input signal such that, when the low-resistance path is enabled, it reduces the transmission resistance for a short period of time.

A signal generation circuit generates first and second non-overlapping digital signals from an input pulse signal. A first digital circuit includes: a first logical OR gate receiving the second digital signal and the input pulse signal to generate a third digital signal; and a second logical OR gate receiving the input pulse signal and a delayed version of the third digital signal to generate the first digital signal. A second digital circuit includes: a first logical AND gate receiving the first digital signal and the input pulse signal to generate a fourth digital signal; and a second logical AND gate receiving the input pulse signal and the fourth digital signal to generate the second digital signal.

The present invention provides a driving system operating in a first or second modes. The driving system includes first and second resistance adjusting circuits, a divider, a controller and a driver. The divider divides a second resistance adjusting signal generated by the second resistance adjusting circuit by a standard value to generate a first control signal. The controller receives the first control signal and generates a second control signal. When the driving system operates in the first mode, the driver receives the second control signal, according to the second control signal, the driver adjusts an output impedance of itself and adjusts equalization amplitude of a first differential output signal generated by itself. When the driving system operates in the second mode, the driver generates a second differential output signal and adjusts the output impedance according to a first resistance adjusting signal generated by the first resistance adjusting circuit.

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

An apparatus can include tracking circuitry coupled to a current source and configured to generate a reference voltage signal based on a reference current signal from the current source. The apparatus can include voltage regulator circuitry coupled to the tracking circuitry and configured to generate a voltage supply signal based on the reference voltage signal. The apparatus can further include amplifier circuitry configured to amplify an input signal based on the voltage supply signal. The reference voltage signal can track process and temperature variations associated with at least one field effect transistor within the tracking circuitry. The voltage regulator circuitry can be configured to operate with a closed loop gain higher than 1. The tracking circuitry includes a first transistor connected in parallel with a second transistor, the first and second transistors having a complimentary type with each other (e.g., NMOS and PMOS transistors).

A calibration circuit includes a reference resistor leg, a calibration code generation circuit, and an emphasis circuit. The reference resistor leg is coupled to an external reference resistor through a reference resistor node, and changes a voltage level of the reference resistor node based on a calibration code. The emphasis circuit accelerates a voltage level change of the reference resistor node based on the calibration code.

An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.