A semiconductor device includes: a voltage clamping circuit including a plurality of first elements operating upon receiving a voltage having a first level and configured to output a clamp signal swinging in the first level by adjusting a voltage of an external input signal swinging in a second level more than twice the first level; a first buffer circuit configured to buffer the clamp signal; a level down shifter circuit configured to reduce the voltage of the clamp signal and output an internal input signal swinging in the first level between a predetermined reference voltage and a first power supply voltage higher than the reference voltage; and a second buffer circuit configured to buffer the internal input signal and transmits the internal input signal to a core circuit.

An output buffer circuit includes an output node, a P-type transistor, an N-type transistor, and a first variable resistor circuit provided in a signal path between a drain of one of the P-type transistor and the N-type transistor and the output node.

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

A method of performing coarse calibration of a voltage-mode (VM) driver having a plurality of driver slices connected in parallel includes setting a control code applied to activated driver slices of the plurality of driver slices to a maximum value to minimize an output resistance of the activated driver slices, activating one driver slice of the plurality of driver slices by applying the control code to the one driver slice, while disabling other driver slices of the plurality of driver slices, measuring an output resistance of the VM driver, determining whether the output resistance of the VM driver is greater than a desired resistance, and in response to determining that the output resistance of the VM driver is greater than a desired resistance activating one more driver slice of the plurality of driver slices.

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

A transmitting device includes a calibration circuit and a transmission circuit. The calibration circuit generates calibration codes by performing a calibration operation. The calibration circuit also generates compensation calibration codes by increasing or decreasing values of the calibration codes according to whether a number of codes among the calibration codes having a predetermined level is greater than or equal to a threshold value. The transmission circuit drives a signal transmission line based on an input signal and the compensation calibration codes.

An operation speed of a voltage conversion circuit is improved without increasing an output level of the voltage conversion circuit. The voltage conversion circuit is provided with a high-voltage side transistor and a gate control unit. In this voltage conversion circuit, the high-voltage side transistor outputs a predetermined high voltage higher than a predetermined reference voltage. Also, in the voltage conversion circuit, the gate control unit generates a predetermined control voltage higher than a predetermined high voltage from an input signal and applies the same between a gate and a source of the high-voltage side transistor, thereby allowing the high-voltage side transistor to output a predetermined high voltage.

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.

One aspect disclosed features an apparatus comprising: an input buffer configured to receive an input voltage pulse as an input, and to output, responsive to a leading edge of the input voltage pulse, a logic high voltage pulse at a first output of the input buffer and a logic low voltage pulse at a second output of the input buffer; an array of L active pull-up devices electrically coupled between a positive supply rail and an output node, each active pull-up device driven by the logic high voltage pulse as modulated by a corresponding bit of a series of N first L-bit binary words; and an array of L active pull-down devices electrically coupled between a negative supply rail and the output node, each active pull-down device driven by the logic low voltage pulse as modulated by a corresponding bit of a series of M second L-bit binary words.