A signal-multiplexing device according to the present embodiment has a structure that is capable of satisfactorily handling an increase in a data rate. The signal-multiplexing device includes M pre-stage buffers and an output buffer. An m-th pre-stage buffer B.sub.m outputs an m-th input signal when the signal levels of both an m-th control signal C.sub.m and an n-th control signal C.sub.n of M control signals are significant, and the m-th pre-stage buffer B.sub.m enters into a high-impedance state when the signal level of at least one of the m-th control signal C.sub.m and the n-th control signal C.sub.n is non-significant. The output buffer B.sub.out sequentially outputs input signals that have been respectively outputted from the M pre-stage buffers at different timings.

Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.

Provided is a ternary logic synthesis method at least temporarily performed by a computer, the ternary logic synthesis method including generating a switching table with respect to pull-up and pull-down circuits using a truth table corresponding to a ternary function, converting the switching table into a sum of products (SOP) using a Quine-McCluskey algorithm, minimizing the SOP, and mapping a transistor corresponding to the SOP.

A scanning driving circuit includes a scanning-level-signal-generation module and a scanning-signal-output-module. The scanning-level-signal-generation module is configured to input an (N1)th stage scanning signal, an (N+1)th stage scanning signal, and a reset signal, generate a scanning level signal based on the (N1)th stage scanning signal, the (N+1)th stage scanning signal, and the reset signal, and hold the scanning level signal. The scanning-signal-output-module, connected to the scanning-level-signal-generation module, is configured to input a clock signal, and configured to output a scanning signal based in the scanning level signal and the clock signal.

An embodiment of a semiconductor package apparatus may include technology to determine declared antenna gain-related information that corresponds to an estimated actual antenna gain for an antenna, and adjust a parameter of a wireless subsystem based on the declared antenna gain-related information. Other embodiments are disclosed and claimed.

Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.

Disclosed is an oscillator including: a digital to analog converter configured to convert a received control code into an analog voltage and output the converted analog voltage; a mirror circuit configured to adjust a current of a common output node to which the analog voltage is applied; and a periodic signal output circuit configured to output a periodic signal having a frequency according to the analog voltage, in which the digital to analog converter, the mirror circuit, and the periodic signal output circuit are implemented with tri-state inverters.

Disclosed is a method comprising determining that a signal is to be provided to a beamformer integrated circuit using a control interface associated with the beamformer integrated circuit, identifying, within, at least one memory, a unique address of the beamformer integrated circuit, wherein the beamformer integrated circuit is aware of own unique address based on a set state of an address pin of the beamformer integrated circuit, wherein the set state of the address pin is one of at least three available set states, the set state being provided as an input to three logical buffers electrically coupled to the beamformer integrated circuit, and outputs from the three logical buffers being combined using a logical encoder that generates the unique address, and providing the signal to the beamformer integrated circuit using the unique address.

Some embodiments include an apparatus having a flip-flop circuit, which can include a first tristate inverter, a second tristate inverter including an input node coupled to an input node of the first tristate inverter; a first additional inverter including, and a second additional inverter including an output node coupled to an output node of the first additional inverter; a first memory including a first memory node coupled to an output node of the second tristate inverter, and a first additional memory node coupled to an input node of the first additional inverter; and a second memory including a second memory node coupled to an output node of the first tristate inverter, and a second additional memory node coupled to an input node of the second additional inverter.

A tunnel field effect transistor includes a constant current formation layer, a source region and a drain region provided on the constant current formation layer, a channel layer provided between the source region and the drain region, a gate electrode provided on the channel layer, and a gate insulating film provided between the gate electrode and the channel layer, wherein the source region and the drain region have different conductivity types, and the constant current formation layer forms a constant current between the drain region and the constant current formation layer.