An embodiment of a semiconductor package apparatus may include technology to determine declared antenna gain-related information that corresponds to an estimated actual antenna gain for an antenna, and adjust a parameter of a wireless subsystem based on the declared antenna gain-related information. Other embodiments are disclosed and claimed.

An integrated circuit for a computer may include a non-binary logic gate circuit configured to perform a logic operation that includes: at least one input terminal; an output terminal; and transistor circuitry configured to: receive, via the at least one input terminal, at least one alternating current (AC) input voltage at three input voltage levels, wherein each of the three input voltage levels corresponds to a respective one of three logic values; and generate, at the output terminal, an output voltage at one or more output voltage levels based on the at least one AC input voltage and the logic operation, wherein each of the one or more output voltage levels corresponds to a respective one of the three logic values.

Disclosed is an oscillator including: a digital to analog converter configured to convert a received control code into an analog voltage and output the converted analog voltage; a mirror circuit configured to adjust a current of a common output node to which the analog voltage is applied; and a periodic signal output circuit configured to output a periodic signal having a frequency according to the analog voltage, in which the digital to analog converter, the mirror circuit, and the periodic signal output circuit are implemented with tri-state inverters.

Three state latch. In accordance with a first embodiment, an electronic circuit includes a single latch having three stable states. The electronic circuit may be configured so that all three outputs reflect a change at any one input in not more than three gate delays. The electronic circuit may further be configured so that when all inputs are set to one, a previous state of the latch is retained and output on the outputs.

A scanning driving circuit includes a scanning-level-signal-generation module and a scanning-signal-output-module. The scanning-level-signal-generation module is configured to input an (N1)th stage scanning signal, an (N+1)th stage scanning signal, and a reset signal, generate a scanning level signal based on the (N1)th stage scanning signal, the (N+1)th stage scanning signal, and the reset signal, and hold the scanning level signal. The scanning-signal-output-module, connected to the scanning-level-signal-generation module, is configured to input a clock signal, and configured to output a scanning signal based in the scanning level signal and the clock signal.

Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.

Provided is a transistor including: a constant current formation layer; a channel layer provided on the constant current formation layer; a pair of source/drain regions spaced apart from each other, with the channel layer therebetween on the constant current formation layer; a gate electrode provided on the channel layer; and a gate ferroelectric film provided between the gate electrode and the channel layer.

Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.

Compact logic evaluation gates are built using null convention logic (NCL) circuits. The inputs to a null convention circuit include a NCL true input and a NCL complement input. The NCL circuit includes a gate coupled to the pair of inputs, where the gate comprises a plurality of transistors. The transistors allow for logical signal capture, provide a pair of cross-coupled inverters for data storage, and include a first and second pull-down device. The first pull-down device causes a first side of the pair of cross-coupled inverters to go to a 0 state when a 1 is applied to the NCL true input, and the second pull-down device causes a second side of the pair of cross-coupled inverters to go to a 0 state when a 1 is applied to the NCL complement input.

A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit having a first current path for receiving a first input signal of a pair of differential input signals and a second current path for receiving a second input signal of the pair of differential input signals, the transmitter driver circuit comprising a tail current path coupled to each of the first current path and the second current path; a first current source coupled between a first reference voltage and ground, wherein a first current of the first current source is proportional to the tail current of the tail current path; a first pull-up current source coupled between the first reference voltage and a first output node of the transmitter driver circuit; and a second pull-up current source coupled between the first reference voltage and a second output node of the transmitter driver circuit. A method of generating a modulated signal in a transmitter of an integrated circuit is also disclosed.