A signal isolation system includes an external device; and a signal isolation circuit, coupled to the external device, including a control circuit, configured to operate the signal isolation circuit in an input mode or an output mode according to a status of the external device; a digital input/output circuit, configured to input/output signal based on the input mode or the output mode determined by the control circuit; and an input/output port, coupled to the digital input/output circuit, configured to be an input port or an output port according to the input mode or the output mode determined by the control circuit.

A signal isolation system includes an external device; and a signal isolation circuit, coupled to the external device, including a control circuit, configured to operate the signal isolation circuit in an input mode or an output mode according to a status of the external device; a digital input/output circuit, configured to input/output signal based on the input mode or the output mode determined by the control circuit; and an input/output port, coupled to the digital input/output circuit, configured to be an input port or an output port according to the input mode or the output mode determined by the control circuit.

A novel programmable logic device is provided. Programmable switches each include a first transistor and a second transistor. The first transistor in a first programmable switch controls conduction between a first wiring and a gate of the second transistor in the first programmable switch. The second transistor in the first programmable switch controls conduction between the first wiring and a second wiring. The first transistor in the second programmable switch controls conduction between another first wiring and a gate of the second transistor in the second programmable switch.

A novel programmable logic device is provided. Programmable switches each include a first transistor and a second transistor. The first transistor in a first programmable switch controls conduction between a first wiring and a gate of the second transistor in the first programmable switch. The second transistor in the first programmable switch controls conduction between the first wiring and a second wiring. The first transistor in the second programmable switch controls conduction between another first wiring and a gate of the second transistor in the second programmable switch.

An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.

An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.

Systems and methods of use and fabrication are described for a THx2 threshold gate cell for a programmable gate array including a mode-independent PMOS configuration and an NMOS configuration configured to operate in one of a TH12 mode and a TH22 mode, wherein x is set to a threshold of 1 for the TH12 mode and x is set to a threshold of 2 for the TH22 mode.

Systems and methods of use and fabrication are described for a THx2 threshold gate cell for a programmable gate array including a mode-independent PMOS configuration and an NMOS configuration configured to operate in one of a TH12 mode and a TH22 mode, wherein x is set to a threshold of 1 for the TH12 mode and x is set to a threshold of 2 for the TH22 mode.

An AND-gate device having a structure arms, a channel from a first arm and a second arm extends to a channel of a third arm. When a current from a first voltage flowing from a first electrode of the first arm to a second electrode of the second arm, a flow of electrons is generated that flows through the third arm channel from the channel of the first and second arms to the third arm channel. At least two input structures are positioned in series in the third arm. Each input structure includes a fin structure having a gate controlled by an individual voltage applied to an electrode which induces an electric-field structure that shifts by an amount of the voltage. The controllable gate opening changes a depletion width, causing an amount of flow of ballistic electrons to pass through the channel. A sensor detects the ballistic electrons.

A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements. In one embodiment, the fully integrated RF switch includes a built-in oscillator, a charge pump circuit, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit. Several embodiments of the charge pump, level shifting, voltage divider, and RF buffer circuits are described. The inventive RF switch provides improvements in insertion loss, switch isolation, and switch compression.