A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements. In one embodiment, the fully integrated RF switch includes a built-in oscillator, a charge pump circuit, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit. Several embodiments of the charge pump, level shifting, voltage divider, and RF buffer circuits are described. The inventive RF switch provides improvements in insertion loss, switch isolation, and switch compression.

Provided is a logic circuit comprising: a switch portion that includes one or more switching devices configured to be turned on and off in accordance with an input signal and is configured to generate an output signal with a logical value according to an operating state of the switching devices; and a clamp portion configured to clamp a voltage of the output signal, of a case where the logical value of the output signal is logic H. The switch portion may be arranged between an output line and a reference potential line, and the clamp portion may be arranged in parallel with the switch portion, between the output line and the reference potential line. The logic circuit may include a current suppression portion configured to suppress a current flowing through the clamp portion, when the logical value of the output signal is logic H.

Provided is a logic circuit comprising: a switch portion that includes one or more switching devices configured to be turned on and off in accordance with an input signal and is configured to generate an output signal with a logical value according to an operating state of the switching devices; and a clamp portion configured to clamp a voltage of the output signal, of a case where the logical value of the output signal is logic H. The switch portion may be arranged between an output line and a reference potential line, and the clamp portion may be arranged in parallel with the switch portion, between the output line and the reference potential line. The logic circuit may include a current suppression portion configured to suppress a current flowing through the clamp portion, when the logical value of the output signal is logic H.

A semiconductor device capable of level shifting in a negative potential direction using an n-channel transistor is provided. The semiconductor device includes a first source follower, a second source follower, and a comparator. The first source follower is supplied with a second high power supply potential and a low power supply potential; the second source follower is supplied with a first high power supply potential and the low power supply potential; and a digital signal which expresses a high level or a low level using the second high power supply potential or the first high power supply potential is input to the first source follower. Here, the second high power supply potential is a potential higher than the first high power supply potential, and the first high power supply potential is a potential higher than the low power supply potential. The comparator compares output potentials of the first source follower and the second source follower and outputs a digital signal which expresses a high level or a low level using the first high power supply potential or the low power supply potential.

An object of the present disclosure is to provide a semiconductor device drive circuit stably preventing an erroneous operation in accordance with an application of dV/dt. A semiconductor device drive circuit includes: pulse transmission circuits outputting an on-pulse transmission signal and an off-pulse transmission signal based on a level shift on-pulse signal and a level shift off-pulse signal; a dV/dt detection circuit detecting a dV/dt period based on the level shift on-pulse signal and the level shift off-pulse signal; a logic filter circuit which does not change outputs when both the on-pulse transmission signal and the off-pulse transmission signal are input; and a latch circuit outputting a signal synchronized with an output of the logic filter circuit. The pulse transmission circuit includes impedance adjusting parts reducing a signal level of the on-pulse transmission signal and the off-pulse transmission signal during the dV/dt period.

An object of the present disclosure is to provide a semiconductor device drive circuit stably preventing an erroneous operation in accordance with an application of dV/dt. A semiconductor device drive circuit includes: pulse transmission circuits outputting an on-pulse transmission signal and an off-pulse transmission signal based on a level shift on-pulse signal and a level shift off-pulse signal; a dV/dt detection circuit detecting a dV/dt period based on the level shift on-pulse signal and the level shift off-pulse signal; a logic filter circuit which does not change outputs when both the on-pulse transmission signal and the off-pulse transmission signal are input; and a latch circuit outputting a signal synchronized with an output of the logic filter circuit. The pulse transmission circuit includes impedance adjusting parts reducing a signal level of the on-pulse transmission signal and the off-pulse transmission signal during the dV/dt period.

A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.

An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

A motor controller system that includes an analog switch multiplexer system is disclosed. Specific implementations include a plurality of field effect transistors (FETs) that may be configured to be operatively coupled with one or more phases of a motor. Each of the plurality of FETs may include a gate, an analog switch multiplexer coupled with each of the gates of the plurality of FETs and with an analog output, and a digital control block coupled with the analog switch multiplexer that may be configured to send a multiplexer select control signal to the analog switch multiplexer in response to receiving a serial peripheral interface signal.