The present application discloses a circuit for generating spread-spectrum synchronous clock signal. The circuit includes a frequency detector comprising a fraction controller configured to compare an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback to generate a first control signal and a second control signal alternately for determining a control word to track the first frequency and a phase-shift controller configured to register n levels for the first control signal and the second control signal to introduce n phase delays for changing a fraction part of the control word randomly to provide a broadened boundary. The circuit also includes a digitally controlled oscillator configured to generate a synthesized periodic signal based on a base time unit, the first frequency, and the control word, with the second frequency being locked within the broadened boundary of the first frequency.

The present application discloses a circuit for generating spread-spectrum synchronous clock signal. The circuit includes a frequency detector comprising a fraction controller configured to compare an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback to generate a first control signal and a second control signal alternately for determining a control word to track the first frequency and a phase-shift controller configured to register n levels for the first control signal and the second control signal to introduce n phase delays for changing a fraction part of the control word randomly to provide a broadened boundary. The circuit also includes a digitally controlled oscillator configured to generate a synthesized periodic signal based on a base time unit, the first frequency, and the control word, with the second frequency being locked within the broadened boundary of the first frequency.

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

The present invention relates to a frequency modulation method based on a phase-locked loop capable of performing fast modulation independent of bandwidth. A frequency modulation system based on a phase-locked loop capable of performing fast modulation independent of bandwidth according to the present invention includes a loop filter including a proportional path and an integral path to determine a bandwidth of a phase-locked loop, a voltage-controlled oscillator configured to adjust a frequency according to an output of the loop filter, and a slope alternator configured to alternate an input current of the loop filter, wherein the slope alternator is located in the integral path of the loop filter to generate an offset current at a moment of change from a modulation rise to a modulation fall.

In some examples, a circuit includes a clock divider and a calibration circuit coupled to the clock divider. The clock divider includes digital-to-time converter (DTC). The calibration circuit configured to determine a gain error and a parametric integrated nonlinearity (INL) error of the DTC, determine a gain adjustment value and a INL adjustment value to compensate for the gain error and the INL error, and modify operation of the DTC according to the gain adjustment value and the INL adjustment value to correct for the gain error and the INL error.

Disclosed are a control signal pulse width extraction-based phase-locked acceleration circuit and a phase-locked loop system, the phase-lock acceleration circuit includes a pulse width extraction control circuit and a current injection switch module; the control output terminal of the pulse width extraction control circuit is connected to the current injection control terminal of the current injection switch module, and the stepping current control terminal of the current injection switch module and the driving input terminal of the pulse width extraction control circuit are both connected to the preset control signal output end of a phase frequency detector for use in controlling, according to pulse width changes of signals outputted by the preset control signal output end, the current injection switch module to inject charges until the phases of a reference clock signal and feedback clock signal inputted by the phase frequency detector are synchronized.

A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.