To improve power converter ON-time generation, an example apparatus includes: a phase frequency detector to determine a phase difference between a first signal and a second signal; a first pulse generator to generate a first time signal at a second time, in which the first signal is associated with a first time delay based on the phase difference; and a second pulse generator coupled to the first pulse generator. The second pulse generator is configured to: generate a second time signal at a third time, in which the third time is after the second time; and obtain a digital word based on the phase difference at a first time, in which the first time is before the second time and the third time, and the second time signal is associated with a second time delay based on the phase difference.

Disclosed is a power supply apparatus including a DC-DC converter implemented as one integrated circuit. A duty of a switching pulse of a DC-DC conversion unit is controlled according to a phase difference between a feedback clock signal and a reference clock signal having a frequency proportional to an output voltage of the DC-DC conversion unit. The duty of the switching pulse may be controlled from an output of a charge pump to be charged and discharged according to the phase difference signal between the feedback clock signal and the reference clock signal.

A hybrid Phase Locked Loop, PLL (10, 34A, 34B, 38) employs an analog control loop during a first period of operation, such as steady-state operation, to achieve a simple design, stable operation at very high frequency, and low phase noise. During a second period of operation, such as frequency changes, a digital control loop takes over. Under digital control, charge pump (14) inputs are forced to be at or near 100% duty cycle for maximum loop filter (16) charging and fast, linear frequency change. The digital control loop monitors when the target frequency is reached, and exits the second period of operation with the proper feedback signal phase. The digital control loop can operate in two control modes. In a first mode, the phase of the divided VCO output signal is synchronized with the phase of a periodic reference signal throughout the frequency change. In a second mode, the frequency and phase are controlled in separate steps, by controlling the integer and fractional parts of delta-sigma generated division number. Three embodiments are disclosed. In a first embodiment, a switch substitutes constant charge pump (14) inputs for the outputs of a phase frequency detector, PFD (12) to maximize the loop filter (16) current. In a second embodiment, one pulse of one of the periodic signals is suppressed, forcing the PFD (12) to output charge pump input signals at near 100% duty cycle. In a third embodiment, all the cycles of one of the periodic signals are suppressed, forcing PFD (12) output signals to 100% duty cycle.

A wide band frequency synthesizer may include a primary phase-locked loop (PLL) to receive a signal that include a local signal and a VCO signal mixed together and to generate the tuning voltage based on a phase comparison of the local signal and the VCO signal. The local signal may be obtained from a reference signal through frequency multiplication. If the primary PLL fails to lock onto an output frequency, a secondary PLL (acquisition circuit) may be switched in performing a phase comparison between the reference signal and the VCO signal to generate the tuning voltage. The secondary PLL may then provide the tuning voltage to an output of the primary PLL.

Some examples described herein provide an integrated circuit comprising an auxiliary clock and data recovery (CDR) circuitry. The CDR circuitry is configured to oversample an incoming data signal and generate a locked clock signal. The auxiliary CDR circuitry may comprise a phase-locked loop (PLL) configured to receive the incoming data signal and generate the locked clock signal. The PLL may comprise a phase detector (PD) configured to receive the incoming data signal and capture a number of samples of the incoming data signal in response to a number of adjacent clock signals and minimum data transition thresholds implemented by an intersymbol interference (ISI) filter, the minimum data transition thresholds identifying minimum data transitions in the incoming data signal.

Voltage-controlled oscillation circuitry includes multiple cores and multiple mode or gain boosters coupled between the multiple cores. To prevent an undesired operating mode of the voltage-controlled oscillation circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), the mode boosters may increase a desired gain of the desired operating mode and decrease an undesired gain of the undesired operating modes. In particular, mode boosters coupled to terminals of the cores that are associated with the desired operating mode may be enabled, while mode boosters coupled to terminals of the cores that are associated with the undesired operating mode may be disabled.

Disclosed is a frequency dividing circuit, a frequency dividing method and a phase locked loop. The frequency dividing circuit comprises: a clock selection unit outputting a first clock signal, select a second clock signal lagging behind the first clock signal by (½-1/M) of one phase; an integer frequency dividing unit performing frequency division on the first clock signal to provide a frequency-divided clock signal; a trigger unit triggering the frequency-divided clock signal according to the second clock signal to obtain a modulation clock signal; a switching signal unit providing a switching signal according to the modulation clock signal and a preset target output frequency. The clock selection unit selects and further outputs a third clock signal as the first clock signal according to the target phase selection information, to adjust the frequency of the frequency-divided clock signal, reduce noise and improve loop bandwidth of the phase locked loop.

The present invention provides a clock signal generation circuit including a global PLL and a plurality of local PLLs. In the operation of the clock signal generation circuit, the global PLL is configured to receives a reference clock signal to generate a synchronization clock signal, and the plurality of local PLLs receive the synchronization clock signal to generate a plurality of clock signals, respectively, and the plurality of clock signals are used to generate a plurality of output clock signals.

The present invention provides a clock signal generation circuit including a global PLL and a plurality of local PLLs. In the operation of the clock signal generation circuit, the global PLL is configured to receives a reference clock signal to generate a synchronization clock signal, and the plurality of local PLLs receive the synchronization clock signal to generate a plurality of clock signals, respectively, and the plurality of clock signals are used to generate a plurality of output clock signals.

A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.