A clock generator calibration system can include a phased-locked loop and a correction circuit. The PLL can generate an output clock signal, and the correction circuit can adjust a frequency signal of the PLL based on a digital signal of the PLL. The digital signal can be generated based on the adjusted frequency signal.

Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader. The card clock recovery system has: a phase lock loop having: a phase/frequency detector, which is configured to receive a reference signal provided at an RX port of a matching network during a receiving mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmission mode of the NFC transceiver, to receive a loop feedback signal, and to provide a phase error signal that represents a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal that is derived from the phase error signal, and to provide a filtered corrected phase error signal; a controllable oscillator, which is configured to receive the filtered corrected phase error signal and to provide a controlled frequency output signal, which is provided as the card clock generation control signal to a card clock generation unit of an NFC card transceiver, and as the loop feedback signal, via the loop feedback line, to the phase/frequency detector. The card clock recovery system further has a phase offset correction unit, which is configured to receive the phase error signal provided by the phase/frequency detector and to provide the corrected phase error signal to the loop filter, and which has a phase error sampling unit, a phase offset computation unit, and a phase subtractor unit.

A digitally controlled oscillator (DCO) includes; a current mirror configured to generate a supply current in response to a bias voltage matching a reference current, a variable resistor connected to the current mirror through a first node outputting the reference current and configured to provide a variable resistance in response to a first control signal, an oscillation circuit connected to the current mirror through a second node outputting the supply current and configured to generate an oscillation signal in response to the supply current, and a feedback circuit configured to control the bias voltage in relation to at least one of a voltage at the first node and a voltage at the second node.

A digitally controlled oscillator (DCO) includes; a current mirror configured to generate a supply current in response to a bias voltage matching a reference current, a variable resistor connected to the current mirror through a first node outputting the reference current and configured to provide a variable resistance in response to a first control signal, an oscillation circuit connected to the current mirror through a second node outputting the supply current and configured to generate an oscillation signal in response to the supply current, and a feedback circuit configured to control the bias voltage in relation to at least one of a voltage at the first node and a voltage at the second node.

A method adapts a resonant frequency of a first filter of a closed control loop to a given frequency. The method includes feeding an output signal of a delta sigma modulator of the closed control loop into a frequency adaptation circuit and determining a first noise spectrum of the output signal in a first frequency band and a second noise spectrum of the output signal in a second frequency band. The first frequency band and the second frequency band are arranged symmetrically with respect to the given frequency. The method includes comparing the first noise spectrum with the second noise spectrum, generating an adaptation signal that causes a frequency adaptation of the resonant frequency if the first noise spectrum differs from the second noise spectrum, and outputting the adaptation signal from the frequency adaptation circuit to a control input of the first filter for adapting the resonant frequency.

A method adapts a resonant frequency of a first filter of a closed control loop to a given frequency. The method includes feeding an output signal of a delta sigma modulator of the closed control loop into a frequency adaptation circuit and determining a first noise spectrum of the output signal in a first frequency band and a second noise spectrum of the output signal in a second frequency band. The first frequency band and the second frequency band are arranged symmetrically with respect to the given frequency. The method includes comparing the first noise spectrum with the second noise spectrum, generating an adaptation signal that causes a frequency adaptation of the resonant frequency if the first noise spectrum differs from the second noise spectrum, and outputting the adaptation signal from the frequency adaptation circuit to a control input of the first filter for adapting the resonant frequency.

Disclosed is a frequency dividing circuit, a frequency dividing method and a phase locked loop. The frequency dividing circuit comprises: a clock selection unit outputting a first clock signal, select a second clock signal lagging behind the first clock signal by (½-1/M) of one phase; an integer frequency dividing unit performing frequency division on the first clock signal to provide a frequency-divided clock signal; a trigger unit triggering the frequency-divided clock signal according to the second clock signal to obtain a modulation clock signal; a switching signal unit providing a switching signal according to the modulation clock signal and a preset target output frequency. The clock selection unit selects and further outputs a third clock signal as the first clock signal according to the target phase selection information, to adjust the frequency of the frequency-divided clock signal, reduce noise and improve loop bandwidth of the phase locked loop.

Disclosed is a frequency dividing circuit, a frequency dividing method and a phase locked loop. The frequency dividing circuit comprises: a clock selection unit outputting a first clock signal, select a second clock signal lagging behind the first clock signal by (½-1/M) of one phase; an integer frequency dividing unit performing frequency division on the first clock signal to provide a frequency-divided clock signal; a trigger unit triggering the frequency-divided clock signal according to the second clock signal to obtain a modulation clock signal; a switching signal unit providing a switching signal according to the modulation clock signal and a preset target output frequency. The clock selection unit selects and further outputs a third clock signal as the first clock signal according to the target phase selection information, to adjust the frequency of the frequency-divided clock signal, reduce noise and improve loop bandwidth of the phase locked loop.

Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307).

Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307).