A dual-loop phase-locking circuit combines a conventional phase-frequency-detector (PFD) and frequency-divider based first loop to lock an output signal frequency to a multiple of a reference signal frequency within a first loop bandwidth BW1 with a second loop to simultaneously lock the output signal phase to a second signal independently locked to the same multiple of the reference signal. The second loop integrates the phase error between the output signal and the second signal, and applies an offset at the PFD output in the first loop to reduce the first loop phase errors within a second loop bandwidth BW2 (<BW1). The first loop bandwidth BW1 can be optimized for overall phase-noise performance of the output signal while retaining the excellent capture and hold characteristics of that loop's topology. The second loop provides superior carrier-frequency phase alignment between the output signal and second signal. The output and second signal may therefore be configured as inputs to systems that require highly coherent carrier signals with de-correlated phase-noise such as phase-noise measurement systems or phase-noise cancellation systems.

One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.

A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.

A semiconductor integrated circuit includes a calibration control circuit configured to generate a setting value for a frequency of a first clock signal, based on a frequency of a second clock signal and a frequency of a third clock signal obtained by dividing the first clock signal by a first frequency division ratio, a phase-locked loop configured to generate a control voltage signal based on a difference in phase between the second and third clock signals, and generate the first clock signal based on the generated control voltage and the setting value, and a determination control circuit configured to determine whether the first and second clock signals are in a locked state, and update the first frequency division ratio based on whether the first and second clock signals are in the locked state.

A semiconductor integrated circuit includes a calibration control circuit configured to generate a setting value for a frequency of a first clock signal, based on a frequency of a second clock signal and a frequency of a third clock signal obtained by dividing the first clock signal by a first frequency division ratio, a phase-locked loop configured to generate a control voltage signal based on a difference in phase between the second and third clock signals, and generate the first clock signal based on the generated control voltage and the setting value, and a determination control circuit configured to determine whether the first and second clock signals are in a locked state, and update the first frequency division ratio based on whether the first and second clock signals are in the locked state.

One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.