A method for producing an output bit stream for a first signal of a first carrier frequency by a security module involves the security module receiving an input signal comprising the first signal and a second signal of a second carrier frequency. A mixed signal is formed which has the first signal at the first carrier frequency, the second signal at the second carrier frequency, and a mixed product at an intermediate frequency. The mixed product is demodulated by a second nonlinear component to output a second baseband signal for generating a second bit stream relating to the first signal in the mixed product. The output logic produces the output bit stream for the first signal, and selects either the first bit stream or the second bit stream as the output bit stream for the first signal.

A method for producing an output bit stream for a first signal of a first carrier frequency by a security module involves the security module receiving an input signal comprising the first signal and a second signal of a second carrier frequency. A mixed signal is formed which has the first signal at the first carrier frequency, the second signal at the second carrier frequency, and a mixed product at an intermediate frequency. The mixed product is demodulated by a second nonlinear component to output a second baseband signal for generating a second bit stream relating to the first signal in the mixed product. The output logic produces the output bit stream for the first signal, and selects either the first bit stream or the second bit stream as the output bit stream for the first signal.

In one aspect, a clock monitor includes a frequency-to-voltage converter (FVC) configured to receive a clock signal and configured to generate a voltage signal in response to the clock signal received. The FVC includes a resistor and a switched capacitor (SC) circuit connected to the resistor to form a resister divider circuit. The switched capacitor circuit includes a capacitor. The clock monitor detects that a clock frequency is zero and/or the clock frequency is not within a frequency range.

In one aspect, a clock monitor includes a frequency-to-voltage converter (FVC) configured to receive a clock signal and configured to generate a voltage signal in response to the clock signal received. The FVC includes a resistor and a switched capacitor (SC) circuit connected to the resistor to form a resister divider circuit. The switched capacitor circuit includes a capacitor. The clock monitor detects that a clock frequency is zero and/or the clock frequency is not within a frequency range.

The physically unclonable function device (DIS) comprises a set of MOS transistors (TR1i, TR2j) mounted in diodes having a random distribution of respective threshold voltages, and comprising N first transistors and at least one second transistor. At least one output node of the function is capable of delivering a signal, the level of which depends on the comparison between a current obtained using a current circulating in the at least one second transistor and a current obtained using a reference current that is equal or substantially equal to the average of the currents circulating in the N first transistors. A first means (FM1i) is configured to impose on each first transistor a respective fixed gate voltage regardless of the value of the current circulating in the first transistor, and a second means (SM2j) is configured to impose a respective fixed gate voltage on each second transistor regardless of the value of the current circulating in the second transistor.

The physically unclonable function device (DIS) comprises a set of MOS transistors (TR1i, TR2j) mounted in diodes having a random distribution of respective threshold voltages, and comprising N first transistors and at least one second transistor. At least one output node of the function is capable of delivering a signal, the level of which depends on the comparison between a current obtained using a current circulating in the at least one second transistor and a current obtained using a reference current that is equal or substantially equal to the average of the currents circulating in the N first transistors. A first means (FM1i) is configured to impose on each first transistor a respective fixed gate voltage regardless of the value of the current circulating in the first transistor, and a second means (SM2j) is configured to impose a respective fixed gate voltage on each second transistor regardless of the value of the current circulating in the second transistor.

A third signal having a phase intermediate between a first signal based on a reference signal and a second signal with a phase shifted by an element of a previous stage is generated, a signal obtained by shifting the phase of the third signal by a first phase shill amount is output as a second signal to an element of a subsequent stage, a phase difference between the third signal and a fourth signal obtained by shifting the phase of a first signal output from the element of the subsequent stage by the first phase shift amount is detected, and the first phase shift amount is controlled on the basis of the detected phase difference.

A third signal having a phase intermediate between a first signal based on a reference signal and a second signal with a phase shifted by an element of a previous stage is generated, a signal obtained by shifting the phase of the third signal by a first phase shill amount is output as a second signal to an element of a subsequent stage, a phase difference between the third signal and a fourth signal obtained by shifting the phase of a first signal output from the element of the subsequent stage by the first phase shift amount is detected, and the first phase shift amount is controlled on the basis of the detected phase difference.

Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.