Embodiments of the present disclosure provide an apparatus including: a phase detector for detecting a write frequency of a deserializer and a read frequency of a serializer, such that the phase detector outputs a first code sequence in response to the write frequency being greater than the read frequency, or a second code sequence at the rotator input in response to the write frequency being less than the read frequency; and a phase rotator for receiving the first code sequence or the second code sequence from the phase rotator to transmit a pacing signal having the read frequency to the deserializer, wherein the pacing signal causes the read frequency to increase or decrease based on whether the read frequency is different from the write frequency.

An integrated circuit (IC) chip including clock generation circuitry to generate a clock signal. Clock interface circuitry is coupled to the clock generation circuitry and includes multiple transmit pins that are distributed across a mounting surface of the IC chip. Each of the multiple transmit pins is configured to transmit a respective version of the clock signal to one or more off-chip devices. Multiple receiver pins are distributed across the mounting surface of the IC chip and correspond to the multiple transmit pins. Each of the multiple receiver pins is configured to receive respective arrival clock signals from the one or more off-chip devices. Delay compensation circuitry is coupled to the clock interface circuitry and includes multiple delay circuits. Each delay circuit is configured to delay a given clock signal fed to a given transmit pin by a given delay value to establish global timing alignment of the arrival clock signals at the one or more external devices.

The disclosure relates to monitoring of feedback systems such as phase lock loops. A system is disclosed, comprising: a feedback circuit (100); and a monitoring module (190). The monitoring module (190) is configured to: i) receive actual values of at least one state variable describing the state of the feedback circuit at a first time; ii) determine a predicted future value of the at least one state variable at a second time from the actual values at the first time using a model of the feedback circuit; iii) receive actual values of the at least one state variable at the second time; iv) compare the predicted future value of the at least one state variable at the second time with the actual value of the at least one state variable at the second time; and v) determine whether the feedback circuit has a fault condition, depending on the results of step iv).

The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.

A frequency synthesizer includes a clock multiplier unit configured to receive a first clock and output a second clock in accordance with a multiplication factor; a divide-by-three circuit configured to receive the second clock and output a third clock; a first divide-by-two circuit configured to receive the second clock and output a fourth clock; a second divide-by-two circuit configured to receive the fourth clock and output a fifth clock; a first multiplexer configured to receive the third clock and the fourth clock and output a seventh clock in accordance with a first selection signal; a second multiplexer configured to receive the third clock and the fifth clock and output an eighth clock in accordance with a second selection signal; and a mixer configured to receive the seventh clock and the eighth clock and output an output clock.

Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO K.sub.DCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.

A signal generating electric circuit, a signal generating method, a digit-to-time converting electric circuit and a digit-to-time converting method. The signal generating electric circuit includes: a first generating electric circuit configured for, based on a first frequency control word and a reference time unit, generating a periodic first output signal; and a second generating electric circuit configured for, based on a second frequency control word and the reference time unit, generating a periodic second output signal. The first frequency control word includes a first integer part and a first fractional part, the second frequency control word includes a second integer part and a second fractional part, the first integer part is equal to the second integer part, the first fractional part and the second fractional part are not equal, and a period of the first output signal and a period of the second output signal are not equal.

An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.

Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.

According to a clock generator, an oscillator outputs source oscillation clocks which are trimmed according to a trimming code. A first frequency divider generates X frequency division clocks by frequency-dividing the source oscillation clocks by a first frequency division ratio X. A trimming controller changes the trimming code within a period of the X frequency division clocks and supplies the changed trimming code to the oscillator.