A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation.

Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.

A digitally controlled oscillator (DCO) that generates an output frequency clock signal without drift and can be rapidly locked to an input or reference clock is described. A variable-modulus-fixed-increment form of DCO is configured to divide the frequency of a nominally fixed frequency oscillator. A constant is derived from the ratio of a fixed increment to the desired output frequency; this constant is multiplied by the frequency of the oscillator and the modulus adjusted to keep the ratio of the input clock and the output clock constant. The frequency of the oscillator is conveniently measured by counting the number of cycles between input cycles of a reference frequency. The oscillator must be greater in frequency than the expected output and is most accurate in cases where the reference frequency is low compared to the expected output frequency.

An element includes a coupling line in which a first conductor layer, a dielectric layer, and a second conductor layer are stacked in this order, and which is connected to the second conductor layer in order to mutually synchronize a plurality of antennas at a frequency of a terahertz wave; and a bias line connecting a power supply for supplying a bias signal to a semiconductor layer and the second conductor layer. A wiring layer in which the coupling line is formed and a wiring layer in which the bias line is formed are different layers. The bias line is disposed in a layer between the first conductor layer and the second conductor layer.

A built-in self-test (BIST) block is provided that is incorporated into an all-digital phase locked loop (ADPLL) located on chip with the ADPLL. The BIST performs testing functions without need for support external to the chip. Test setup, test control, and test evaluation are performed entirely on chip. The BIST provides information regarding success or failure of the testing and can provide error information regarding test cases that do not pass successfully.

Disclosed is a fast lock phase-locked loop circuit for avoiding cycle slip, which belongs to the technical field of integrated circuits. The fast lock phase-locked loop circuit includes a phase frequency detector, a charge pump, an intermediate stage circuit, a loop filter, a voltage-controlled oscillator and a frequency divider. The phase frequency detector, the charge pump, the intermediate stage circuit, the loop filter and the voltage-controlled oscillator are connected in sequence; an output OUT end of the voltage-controlled oscillator is connected with an input IN end of frequency divider, and an output OUT end of the frequency divider is connected with an input IN end of the phase frequency detector to form a feedback path. The output clock frequency of the VCO and the expected frequency, i.e., the reference clock frequency and the feedback clock frequency, are prevented from being too close when the loop is started.

An element includes a coupling line in which a first conductor layer, a dielectric layer, and a second conductor layer are stacked in this order, and which is connected to the second conductor layer in order to mutually synchronize a plurality of antennas at a frequency of a terahertz wave; and a bias line connecting a power supply for supplying a bias signal to a semiconductor layer and the second conductor layer. A wiring layer in which the coupling line is formed and a wiring layer in which the bias line is formed are different layers. The bias line is disposed in a layer between the first conductor layer and the second conductor layer.

Disclosed are a control signal pulse width extraction-based phase-locked acceleration circuit and a phase-locked loop system, the phase-lock acceleration circuit includes a pulse width extraction control circuit and a current injection switch module; the control output terminal of the pulse width extraction control circuit is connected to the current injection control terminal of the current injection switch module, and the stepping current control terminal of the current injection switch module and the driving input terminal of the pulse width extraction control circuit are both connected to the preset control signal output end of a phase frequency detector for use in controlling, according to pulse width changes of signals outputted by the preset control signal output end, the current injection switch module to inject charges until the phases of a reference clock signal and feedback clock signal inputted by the phase frequency detector are synchronized.

Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.

Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.