A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

In an imaging system, a differential signal transmission circuit is configured to output a first signal to a first signal line in an image output period and is configured to output a second signal to a second signal line in the image output period. The first signal and the second signal are included in a differential signal. A signal output circuit is configured to output a second clock signal to the first signal line in a blanking period different from the image output period and is configured to output a second control signal to the second signal line in the blanking period. In a PLL, connection between a charge pump and a loop filter is controlled on the basis of the second control signal output to the second signal line.

A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period, a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

An apparatus is comprised of a processor, a fast-locking Phase-Locked Loop Waveform Generator (PLLWG), an amplifier circuit, and a voltage controlled oscillator (VCO). The processor generates data program signals to program the PLLWG and generates a trigger command signal instructing the PLLWG to generate an analog tuning signal. The PLLWG, coupled to the processor, generates the analog tuning signal based on the trigger command signal. The amplifier circuit, coupled to the PLLWG, receives the analog tuning signal, amplify the analog tuning signal, and generates a control voltage. The VCO, coupled to the amplifier circuit, receives the control voltage and amplifies the control voltage to generate an amplified Radio Frequency (RF) channel frequency signal.

A control unit for generating a plurality of synchronized radio frequency (RF) output signals (RF.sub.out,i) each having a respective output frequency (f.sub.i), phase (Φ.sub.i), and amplitude (A.sub.i), including a signal comparator configured to compare a reference signal having a reference frequency (f.sub.ref) and a reference phase (Φ.sub.ref) with a feedback signal having a feedback frequency (f.sub.PLL) and a feedback phase (Φ.sub.PLL), and configured to generate an error signal representative of a difference between the reference signal and the feedback signal; and a data processing unit receiving as an input signal the error signal generated by the signal comparator, and outputting a plurality of waveform tuning signals (FTW.sub.PLL, FTW.sub.i) as a function of the error signal; wherein a plurality of waveform generators (DDS.sub.PLL, DDS.sub.i) each receiving at least one of the plurality of waveform tuning signals (FTW.sub.PLL, FTW.sub.i) output by the data processing unit, wherein each waveform generator (DDS.sub.PLL, DDS.sub.i) generates a time-dependent amplitude signal (A.sub.PLL(t), A.sub.i(t)) as a function of the received respective waveform tuning signal (FTW.sub.PLL, FTW.sub.i), wherein one predetermined amplitude signal (A.sub.PLL(t)) of the generated plurality of amplitude signals (A.sub.PLL(t), A.sub.i(t)) represents the feedback signal input to the signal comparator, and the other amplitude signals (A.sub.i(t)) represent the respective radio frequency (RF) output signals (RF.sub.out,i) to be generated, and wherein the data processing unit is configured to adjust both the waveform tuning signal (FTW.sub.PLL) corresponding to the one predetermined amplitude signal (A.sub.PLL(t)) representing the feedback signal such as to minimize the error signal, and the other waveform tuning signals (FTW.sub.i) corresponding to the other amplitude signals (A.sub.i(t)) representing the radio frequency (RF) output signals (RF.sub.out,i) based on the adjusted waveform tuning signal (FTW.sub.PLL) of the predetermined amplitude signal (A.sub.PLL(t)) representing the feedback signal.

The disclosure further describes a radio frequency (RF) power generator, an arrangement of at least two such radio frequency (RF) power generators, and a method each for generating a plurality of synchronized radio frequency (RF) output signals (RF.sub.out,i).

An apparatus is comprised of a processor, a fast-locking Phase-Locked Loop Waveform Generator (PLLWG), an amplifier circuit, and a voltage controlled oscillator (VCO). The processor generates data program signals to program the PLLWG and generates a trigger command signal instructing the PLLWG to generate an analog tuning signal. The PLLWG, coupled to the processor, generates the analog tuning signal based on the trigger command signal. The amplifier circuit, coupled to the PLLWG, receives the analog tuning signal, amplify the analog tuning signal, and generates a control voltage. The VCO, coupled to the amplifier circuit, receives the control voltage and amplifies the control voltage to generate an amplified Radio Frequency (RF) channel frequency signal.

Some examples relate to a frequency synthesizer. The frequency synthesizer includes an oscillator including an input terminal and an output terminal. A frequency locked-loop or phase-locked loop (FLL/PLL) unit is arranged on a feedback path extending between the output terminal of the oscillator and the input terminal of the oscillator. A switching unit is configured to selectively switch between a first mode of operation in which the feedback path is closed and the FLL/PLL unit is coupled to the input terminal of the oscillator, and a second mode of operation in which the feedback path is open and a ramping unit is coupled to the input terminal of the oscillator while the feedback path is open.

An all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern generator adapted to generate a frequency control word (FCW) based on a predefined setting and a system clock. In addition, the ADPLL comprises a phase accumulator adapted to translate the FCW into a phase trajectory. The ADPLL further comprises a phase comparator adapted to generate a phase error signal representing a difference between the phase trajectory and the phase of an output oscillation frequency. Moreover, the ADPLL comprises a controller adapted to control a phase of the output oscillation frequency with respect to the phase trajectory.

A receiver is provided having a two-point-modulated phase-locked loop for the rapid scanning of the signal strength of a plurality of frequency channels. The two-point modulation includes a modulation of a frequency gain by an oscillator in the phase-locked loop and a modulation of a frequency division by a divider in the phase-locked loop.

A receiver is provided having a two-point-modulated phase-locked loop for the rapid scanning of the signal strength of a plurality of frequency channels. The two-point modulation includes a modulation of a frequency gain by an oscillator in the phase-locked loop and a modulation of a frequency division by a divider in the phase-locked loop.