A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.

In an imaging system, a differential signal transmission circuit is configured to output a first signal to a first signal line in an image output period and is configured to output a second signal to a second signal line in the image output period. The first signal and the second signal are included in a differential signal. A signal output circuit is configured to output a second clock signal to the first signal line in a blanking period different from the image output period and is configured to output a second control signal to the second signal line in the blanking period. In a PLL, connection between a charge pump and a loop filter is controlled on the basis of the second control signal output to the second signal line.

Systems, methods, and circuitries are provided for resonator-based local oscillator signal generation for receiving self-interference signals. An interference cancellation system for a transceiver includes a resonator configured to generate a high-frequency signal and a local oscillator circuitry. The local oscillator circuitry includes a digital-to time converter configured to receive the high-frequency signal and, in response, generate a clock signal for receiving an interfering signal having an interference frequency. Digital cancellation circuitry is configured to adapt operation of the transceiver based, at least in part, on the received interfering signal.

A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period, a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.

Phase variations between a transmitter (TX) waveform and a receiver (RX) waveform produced by a TX Phase-Locked-Loop (PLL) and a RX PLL, respectively, is a source of error in processing delay calibration used, e.g., in Round Trip Time (RTT) estimation. While a TX waveform and a RX waveform have a constant phase delay while in steady state conditions, during transient times, e.g., at start up or reset, the phase delay may vary by as much as 180, which at baseband frequencies of 50 MHz, introduces a random delay variations of as much as 10 nsec, which is undesirable for fine position estimation using RTT. The phase delay variation between the TX waveform and RX waveform may be reduced or eliminated using a phase correction signal generated using the output signals of the TX PLL and RX PLL.

Phase variations between a transmitter (TX) waveform and a receiver (RX) waveform produced by a TX Phase-Locked-Loop (PLL) and a RX PLL, respectively, is a source of error in processing delay calibration used, e.g., in Round Trip Time (RTT) estimation. While a TX waveform and a RX waveform have a constant phase delay while in steady state conditions, during transient times, e.g., at start up or reset, the phase delay may vary by as much as 180, which at baseband frequencies of 50 MHz, introduces a random delay variations of as much as 10 nsec, which is undesirable for fine position estimation using RTT. The phase delay variation between the TX waveform and RX waveform may be reduced or eliminated using a phase correction signal generated using the output signals of the TX PLL and RX PLL.

A delay-locked loop includes a phase detector configured to detect a phase difference between a first clock and a second clock, a charge pump configured to increase a charge amount at a capacitive load in accordance with a first charge amount and decrease the charge amount at the capacitive load in accordance with a second charge amount based on a phase difference provided by the phase detector, a sample and hold circuit configured to receive the charge amount from the capacitive load and hold the charge amount, and a voltage control delay line configured to select a delay amount based on the charge amount received from the sample and hold circuit. At least one parameter of the delay-locked loop is configured such that a desired pump current ratio of a delay cell is achieved by adjusting a delay amount of the delay cell and/or an amount of current coupled to the delay cell.

In an oscillator device that outputs a frequency signal based on an oscillation frequency of a crystal resonator and a frequency setting value, a frequency difference detector that obtains a difference value corresponding to a frequency difference between the output frequency of the oscillator device and an external clock signal and a temperature detector are disposed. An aging coefficient and a temperature characteristic coefficient are obtained based on a secular change of the difference value obtained in the frequency difference detector and a secular change of the detected temperature during a period where the external clock signal is obtained. Furthermore, a frequency correction value is calculated using the aging coefficient and the temperature characteristic coefficient during a holdover period, and the frequency correction value is added to the frequency setting value.

An oscillator includes a first container that includes a first base substrate and a first lid bonded to the first base substrate and has a first internal space, a second container that is accommodated in the first internal space and fixed to the first base substrate, a resonator element that is accommodated in the second container, a temperature sensor that is accommodated in the second container, a first circuit element that is accommodated in the second container and includes an oscillation circuit oscillating the resonator element and generating an oscillation signal on which temperature compensation is performed based on a detected temperature of the temperature sensor, and a second circuit element that is fixed to the first base substrate and includes a frequency control circuit that controls a frequency of the oscillation signal, in which the second container and the second circuit element are arranged side by side in plan view.