Aspects of this disclosure relate to a VLIF receiver with automatic phase noise adjustment. The presence of an interfering signal is sensed within a bandwidth around a desired channel frequency. Then the local oscillator phase noise is automatically adjusted to optimize blocking. The phase noise adjustment includes increasing the bandwidth of a phase-locked loop.

An oscillator includes a first container that includes a first base substrate and a first lid bonded to the first base substrate and has a first internal space, a second container that is accommodated in the first internal space and fixed to the first base substrate, a resonator element that is accommodated in the second container, a temperature sensor that is accommodated in the second container, a first circuit element that is accommodated in the second container and includes an oscillation circuit oscillating the resonator element and generating an oscillation signal on which temperature compensation is performed based on a detected temperature of the temperature sensor, and a second circuit element that is fixed to the first base substrate and includes a frequency control circuit that controls a frequency of the oscillation signal, in which the second container and the second circuit element are arranged side by side in plan view.

An oscillator arrangement having an oscillator configured to generate an oscillation signal having two half-cycles, an input configured to receive a synchronization signal including synchronization triggers, a synchronizer configured to reject a synchronization trigger received during a first part of a half-cycle and to synchronize the oscillator to a synchronization trigger received during a second part of the half-cycle, and a controller configured to prolong the second part of the half-cycle in response to receiving a synchronization trigger during the first part of the half-cycle.

A method for initializing a phase adder circuit including a multiplier circuit with its two inputs receiving signals of frequency f.sub.o, a mixer circuit, an amplifier circuit, a low pass loop filter, and a voltage controlled oscillator (VCO), the method including: during a first phase, determining a reference voltage which when applied to the VCO causes it to produce a signal having a frequency of nf.sub.0; during a second phase, supplying a signal of frequency nf.sub.o to a first input of the mixer and a signal of frequency (nf.sub.o+f) to a second input of the mixer; and determining an adjustment signal which when applied to the amplifier circuit causes the amplifier circuit to output a signal having a DC component equal to the reference voltage; and during a third phase, forming a primary phase locked loop (PLL) circuit including the mixer, the amplifier circuit, the low pass loop filter and the VCO; and applying the adjustment signal to the amplifier circuit.

A clock generator and an image sensor including the same are disclosed, which relate to technology for improving an operation speed of a voltage controlled oscillator. The clock generator includes a phase frequency detector (PFD) configured to detect a phase difference between a clock signal and a reference clock signal, a voltage converter configured to adjust a current corresponding to a voltage level in response to an output signal of the phase frequency detector (PFD), a filter circuit configured to generate a control voltage by filtering an output signal of the voltage converter, a voltage pumping circuit configured to pump an output voltage of the voltage converter, and provide the control voltage having a pumped voltage level, and a voltage controlled oscillator configured to generate a clock signal, an oscillation frequency of which is adjusted, in response to the control voltage.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.

A clock generation apparatus includes a pulse generator configured to generate a pulse signal and a selection signal using a reference clock signal, a delay line circuit, a switch and a controller. The delay line circuit selects, as an input signal to a delay path, the pulse signal or a fed back portion of a delay clock signal at an output of the delay path, where the selection is based on the selection signal; and thereby generates the delay clock signal. The switch switches a first voltage or a second voltage to the delay line circuit for its operation, where the first voltage further provides power to the pulse generator. The second voltage is generated based on a phase difference between the reference clock signal and the delay clock signal. The controller generates a switch control signal based on a frequency of the delay clock signal.

An oscillator subsystem included in a phase-locked loop circuit of a computer system may include coarse and fine-tuning circuits. The coarse-tuning circuit may generate a coarse-tuning current based on a reference voltage, and the fine-tuning circuit may generate a fine-tuning current by combining respective currents generated by first and second complement current mirror circuits using a voltage level of a control signal. An oscillator circuit may generate a clock signal whose frequency is based on a combination of the coarse and fine-tuning circuits.

Conventional signal sources each have a disadvantage that the noise in a control voltage of a VCO increases, thereby deteriorating the phase noise of an output signal of the signal source.

A signal source of the present invention includes: a reference signal source for outputting a reference signal; a phase frequency comparator for detecting a phase difference between the reference signal and an oscillation signal and outputting a signal corresponding to the phase difference; a filter for filtering the signal output by the phase frequency comparator; an oscillator for outputting the oscillation signal depending on the signal filtered by the filter; and an S/H circuit for receiving a clock signal for controlling a phase of the oscillation signal by controlling sampling operation and holding operation, sampling at least one of the oscillation signal and the reference signal in synchronization with the clock signal, and outputting at least one of the sampled reference signal and the sampled oscillation signal to the phase frequency comparator, the S/H circuit disposed between the oscillator and the phase frequency comparator or between the reference signal source and the phase frequency comparator.