An integrated circuit includes phase locked loop (PLL) circuitry, voltage controlled oscillator (VCO) circuitry, and interface circuitry. The PLL circuitry includes a reference signal input terminal, a reference frequency divider circuit, a reference signal output terminal, a switch, a phase detector, a charge pump, and a control voltage output terminal. The reference frequency divider circuit is coupled to the reference signal input terminal. The switch is coupled to the reference frequency divider circuit and to the reference signal output terminal. The switch is configured to switchably connect the reference frequency divider circuit to the reference signal output terminal. The VCO circuitry includes a control voltage input terminal, a VCO, calibration circuitry, and a calibration input/output (I/O) terminal. The VCO is coupled to the control voltage input terminal. The calibration circuitry is coupled to the VCO. The calibration I/O terminal is coupled to the calibration circuitry.

A delay locked-loop includes, in part, a phase/frequency detector responsive to a reference clock signal, a charge pump responsive to the phase/frequency detector, a variable delay line responsive to an output of the charge pump to cause a delay in the reference clock signal thereby to generate an internal clock signal, and a controlled delay line that includes a multitude of fixed delay cells. The controlled delay line causes the internal clock signal to be delayed by a delay across one of the multitude of fixed delay cells in response to the output of the charge pump. The controlled delay line generates the output clock signal of the delay-locked loop. The delay locked-loop may further include an overflow detector configured to cause the selection of one of the multitude of fixed delays in response to the output of the charge pump.

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.

A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.

A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

A voltage controlled oscillator (VCO) circuit and method achieves linearized frequency tuning over an extended range of analog tuning voltage by implementing a magnetic balun/transformer for biasing and coupling varactor elements. An active negative transconductance circuit of cross-coupled transistors have drains connected with a resonant tank circuit and at least a first varactor element having ends connected to respective first ends of respective first coils of a respective first and second magnetic balun. Respective second ends of respective first coils of respective first and second baluns are connected to a first reference supply voltage. A second varactor element has ends connecting respective first ends of respective second coils of said first and second baluns. A sinking of a bias current through the resonant tank circuit and the transconductance circuit generates an oscillating signal. A calibration method achieves precise VCO gain over wide tuning voltage range, thereby enhancing VCO linearity.

Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.

Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.