The variation of the oscillation frequency of an oscillator can be suppressed even in the case where the amount of interference with the oscillator accompanied by an amplifying operation of a power amplifier and the polarity are not constant. An oscillator is configured to be capable of oscillating at an oscillation frequency in accordance with control signals Vcont and FREQ_CTRL. A phase locked loop allows the oscillator to output an oscillation signal Vout in synchronization with a reference signal RELCLK using the control signal Vcont. A power amplifier amplifies the electric power of the oscillation signal Vout. A variation detection unit detects a variation with respect to the time change of the control signal Vcont after an amplifying operation is started by the power amplifier causing 3interference with the oscillator. A variation correction unit generates the control signal FREQ_CTRL on the basis of the variation detected by the variation detection unit, and corrects the variation of the oscillation frequency caused by the interference accompanied by the amplifying operation of the power amplifier.

The variation of the oscillation frequency of an oscillator can be suppressed even in the case where the amount of interference with the oscillator accompanied by an amplifying operation of a power amplifier and the polarity are not constant. An oscillator is configured to be capable of oscillating at an oscillation frequency in accordance with control signals Vcont and FREQ_CTRL. A phase locked loop allows the oscillator to output an oscillation signal Vout in synchronization with a reference signal RELCLK using the control signal Vcont. A power amplifier amplifies the electric power of the oscillation signal Vout. A variation detection unit detects a variation with respect to the time change of the control signal Vcont after an amplifying operation is started by the power amplifier causing 3interference with the oscillator. A variation correction unit generates the control signal FREQ_CTRL on the basis of the variation detected by the variation detection unit, and corrects the variation of the oscillation frequency caused by the interference accompanied by the amplifying operation of the power amplifier.

A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

The disclosure discloses a coarse adjustment cell array applied to a digitally controlled oscillator and a related apparatus. The coarse adjustment cell array applied to the digitally controlled oscillator includes X coarse adjustment cells, and each coarse adjustment cell in the coarse adjustment cell array includes a logic cell and W fine adjustment cells; and input to a logic cell of a coarse adjustment cell i in the coarse adjustment cell array includes Y coarse adjustment control bits and W fine adjustment control bits, output from the logic cell of the coarse adjustment cell i is used to control whether W fine adjustment cells in the coarse adjustment cell i work, Y is an integer greater than 1, and X and W are integers greater than 1.

A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode.

Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.

Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.

A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.

A delay circuit includes a delay line configured to output an output signal by imposing a delay value on an input signal. The delay circuit further includes an arithmetic unit configured to calculate a control code for the delay value based on delay codes. The delay circuit further includes a delay locked loop (DLL) configured to generate the delay codes based on a clock signal. The delay circuit further includes a controller configured to suspend operation of the DLL when the clock signal operates at a first frequency, to set the DLL to operate based on a second frequency when the DLL is suspended, and to resume operation of the DLL when the clock signal operates at the second frequency without the need to relock the DLL.