A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.

In a PLL circuit, first an ILFD is connected to an output voltage Vtune from an LPF, thereby causing the ILFD to operate as an oscillator. The ILFD, a DIV, PFD, CP, and LPF form a PLL and thereby locking operations are initiated. When a predetermined time elapses, an output frequency from the ILFD converges into a certain value and the PLL is subjected to a locked state. After the locked state is reached, a sample hold circuit SH holds the output voltage Vtune from the loop filter as of that time and frequency adjustment of the ILFD is completed. Similar frequency adjustment is sequentially performed on other ILFDs.

A method for changing a bitwidth of an FPGA configuration for an FPGA, the FPGA configuration having a plurality of at least 2.sup.n bit-containing data signals with nε and ≥3, and the method having the step: when a threshold of a current consumption and/or a temperature of the FPGA is exceeded and/or a replacement signal is present, replacing k least significant bits of the data signals in each case with a zero with kε and ≥2 during an execution of the FPGA configuration on the FPGA.

A method for changing a bitwidth of an FPGA configuration for an FPGA, the FPGA configuration having a plurality of at least 2.sup.n bit-containing data signals with nε and ≥3, and the method having the step: when a threshold of a current consumption and/or a temperature of the FPGA is exceeded and/or a replacement signal is present, replacing k least significant bits of the data signals in each case with a zero with kε and ≥2 during an execution of the FPGA configuration on the FPGA.

A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.

Apparatus and methods for adjusting a gain of an electronic oscillator, such as a voltage-controlled oscillator (VCO), are disclosed. In one aspect, an apparatus for compensating for VCO gain variations includes a charge pump controller. The charge pump controller can be configured to select a VCO gain model based on a comparison of a VCO gain indicator and a threshold value stored in a memory, obtain VCO gain model parameters from the memory corresponding to the selected VCO gain model, and compute a charge pump current control value using the VCO gain model parameters. The charge pump current control value can be used to compensate for VCO gain variations.

A phase locked loop system has a voltage-controlled variable-load ring oscillator (VLCO) that operates in a frequency band determined by a selected load on each stage of the ring oscillator. Each stage of the VLCO has multiple load selection transistors, each coupled to a load capacitor. Apparatus is provided for driving the load selection transistors according to a load configuration; and apparatus is provided for determining an operating load configuration such that a period of a divided reference signal approximately matches a period of a divided VLCO signal with the VLCO control voltage input clamped to a reference voltage. Once the load configuration is set, the loop is allowed to lock. In a particular embodiment, devices are provided for slowly tweaking the VLCO load to help keep the VLCO operating near an optimum control voltage despite drift of circuit parameters with temperature or time.

The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.

A biological information measurement apparatus includes a phase/frequency comparison unit that outputs a deviation signal based on a phase difference between a biological signal and an oscillation signal; a variable loop filter that varies a cutoff frequency and a phase margin and that selectively blocks a signal of a predetermined frequency band contained in the deviation signal; and a voltage controlled oscillation unit that generates the oscillation signal in accordance with the deviation signal that has passed through the variable loop filter. The apparatus further includes a CPU that estimates a SN ratio of the biological signal and analyzes a phase difference/frequency difference between the biological signal outputted from the comparison unit and the oscillation signal. The CPU further changes a constant of the variable loop filter based on the SN ratio and the phase difference/frequency difference.

A biological information measurement apparatus includes a phase/frequency comparison unit that outputs a deviation signal based on a phase difference between a biological signal and an oscillation signal; a variable loop filter that varies a cutoff frequency and a phase margin and that selectively blocks a signal of a predetermined frequency band contained in the deviation signal; and a voltage controlled oscillation unit that generates the oscillation signal in accordance with the deviation signal that has passed through the variable loop filter. The apparatus further includes a CPU that estimates a SN ratio of the biological signal and analyzes a phase difference/frequency difference between the biological signal outputted from the comparison unit and the oscillation signal. The CPU further changes a constant of the variable loop filter based on the SN ratio and the phase difference/frequency difference.