Example implementations relate to partitioning a radio into chains to scan channels. In some examples, a network device may comprise a processing resource and a memory resource storing machine-readable instructions to partition a default radio of the network device into a service chain and a scan chain in response to a scan request, scan a particular channel with the scan chain to discover devices operating on the particular channel of a network, and combine the service chain and the scan chain into the default radio.

An imaging apparatus allows a clock data recovery device to reestablish reception of data even when the clock data recovery device has failed to lock a phase. A reception unit includes a locking unit configured to perform a locking operation for receiving the data and a detection unit configured to detect a lock state of the locking unit. A control unit controls performing of the locking operation again by the locking unit in a case where a lock is not achieved, based on a detection result detected by the detection unit.

An imaging apparatus allows a clock data recovery device to reestablish reception of data even when the clock data recovery device has failed to lock a phase. A reception unit includes a locking unit configured to perform a locking operation for receiving the data and a detection unit configured to detect a lock state of the locking unit. A control unit controls performing of the locking operation again by the locking unit in a case where a lock is not achieved, based on a detection result detected by the detection unit.

Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.

A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.

A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.

Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.

Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.

Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.

Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.