Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.

An all digital phase locked loop system for tracking a variable frequency input signal and method of operation are described. The ADPLL system includes a digital phase locked loop, including a digitally controlled oscillator, and a model of the digitally controller oscillator. The model represents the behaviour of the digitally controlled oscillator as a function of frequency and has a model input arranged to receive a signal indicating a current target frequency. The model is configured to output at least one control signal to control the frequency of the digitally controlled oscillator to be closer to the current target frequency. The digital phase locked loop is configured to control the digitally controlled oscillator to reduce any difference between the frequency of the digitally controlled oscillator and the current target frequency arising from any deviation of the model of the digitally controlled oscillator from the digitally controlled oscillator.

An all digital phase locked loop system for tracking a variable frequency input signal and method of operation are described. The ADPLL system includes a digital phase locked loop, including a digitally controlled oscillator, and a model of the digitally controller oscillator. The model represents the behaviour of the digitally controlled oscillator as a function of frequency and has a model input arranged to receive a signal indicating a current target frequency. The model is configured to output at least one control signal to control the frequency of the digitally controlled oscillator to be closer to the current target frequency. The digital phase locked loop is configured to control the digitally controlled oscillator to reduce any difference between the frequency of the digitally controlled oscillator and the current target frequency arising from any deviation of the model of the digitally controlled oscillator from the digitally controlled oscillator.

An apparatus is disclosed for relocking of a locked loop. In an example aspect, the apparatus includes a locked loop, and the locked loop includes a loop and a locked-loop controller that is coupled to the loop. The loop is configured to run responsive to a run signal. The loop includes a memory state component and signal characteristic adjustment circuitry coupled to the memory state component. The signal characteristic adjustment circuitry is configured to produce an output signal having a characteristic that is based on the memory state component. The locked-loop controller is configured to receive an external power mode signal (EPMS). The locked-loop controller is also configured to generate the run signal to have an enable value at a first time when the EPMS is indicative of an external normal mode and at a second time when the EPMS is indicative of an external standby mode.

Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.

Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.

The disclosure provides a radar apparatus. The radar apparatus includes a transmit unit that generates a first signal in response to a reference clock and a feedback clock. The first signal is scattered by one or more obstacles to generate a second signal. A receive unit receives the second signal and generates N samples corresponding to the second signal. N is an integer. A conditioning circuit is coupled to the transmit unit and the receive unit. The conditioning circuit receives the N samples corresponding to the second signal, and generates N new samples using an error between the feedback clock and the reference clock.

A method of calibrating a digitally controlled oscillator (DCO). The method comprises configuring a fine tuning capacitive component of the DCO into a minimum capacitance configuration therefor, configuring a coarse tuning capacitive component of the DCO into a first configuration therefor and determining a resulting first output frequency of the DCO. The method further comprises configuring the coarse tuning capacitive component into a second configuration therefor, the second and first configurations of the coarse tuning capacitive component being capacitively increasing consecutive configurations respectively, configuring the fine tuning capacitive component into a maximum capacitance configuration therefor, determining control signal settings for a resolution adjustment component of the DCO that achieve a resulting output frequency of the DCO equal to the determined first output frequency, and generating calibration data for the second configuration of the coarse tuning capacitive component comprising the determined control signal settings for the resolution adjustment component.

A method of calibrating a digitally controlled oscillator (DCO). The method comprises configuring a fine tuning capacitive component of the DCO into a minimum capacitance configuration therefor, configuring a coarse tuning capacitive component of the DCO into a first configuration therefor and determining a resulting first output frequency of the DCO. The method further comprises configuring the coarse tuning capacitive component into a second configuration therefor, the second and first configurations of the coarse tuning capacitive component being capacitively increasing consecutive configurations respectively, configuring the fine tuning capacitive component into a maximum capacitance configuration therefor, determining control signal settings for a resolution adjustment component of the DCO that achieve a resulting output frequency of the DCO equal to the determined first output frequency, and generating calibration data for the second configuration of the coarse tuning capacitive component comprising the determined control signal settings for the resolution adjustment component.

The disclosure provides a radar apparatus. The radar apparatus includes a transmit unit that generates a first signal in response to a reference clock and a feedback clock. The first signal is scattered by one or more obstacles to generate a second signal. A receive unit receives the second signal and generates N samples corresponding to the second signal. N is an integer. A conditioning circuit is coupled to the transmit unit and the receive unit. The conditioning circuit receives the N samples corresponding to the second signal, and generates N new samples using an error between the feedback clock and the reference clock.