A circuit device includes an oscillation signal generation circuit that generates an oscillation signal by using a resonator and a processing circuit that estimates an aging characteristic of the oscillation frequency of the resonator based on the result of comparison between the phase of a reference signal based on a satellite signal transmitted from a navigation satellite and the phase of a clock signal based on the oscillation signal. The processing circuit estimates the aging characteristic based on an index value representing the reliability of the state of the received satellite signal and the result of the phase comparison.

A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.

The present invention is related to a clock generating device for generating an internal clock signal having a frequency correlated with a clock frequency of an external oscillator when the clock frequency of the external oscillator is not specified in advance. A clock generating device 105 comprises a memory 134 and a PLL circuit 120. The memory 134 is configured to store information about a frequency of an external clock signal generated by an external oscillator 200 at a predetermined timing. The PLL circuit 120 generates a second clock signal correlated with a first clock signal based on the information stored in the memory 134.

A circuit device includes a processing circuit and an oscillation signal generation circuit. The processing circuit performs Kalman filter processing for a result of phase comparison between an input signal based on an oscillation signal and a reference signal and performs loop filter processing for the result of phase comparison. The oscillation signal generation circuit generates the oscillation signal of an oscillation frequency set by frequency control data which is output data of the loop filter processing by using the frequency control data and a resonator. The processing circuit estimates a truth value for an observed value of the result of phase comparison by using the Kalman filter processing.

A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.

Methods and systems for synchronizing at least one remote local oscillator with a central local oscillator, comprising receiving a remote local oscillator signal from at least one remote local oscillator and a master local oscillator signal from the central local oscillator and in response determining a round-trip phase measurement of temporal delay variability of the duplex real-time link between the remote station and central station, measuring frequency vs. time of the remote local oscillator signal relative to the master oscillator, adjusting the measured frequency vs. time according to the round-trip phase measurement to remove effects of temporal delay variability over the duplex real-time link telemetry, digitally filtering the measured frequency to remove variations in frequency on timescales<10? the round-trip delay and that are known not to be intrinsically due to the remote local oscillator, generating a phase increment signal from the filtered measured frequency, receiving and adjusting the local oscillator signal according to the phase increment signal and in response generating a derived digital domain clock signal that tracks the master local oscillator signal and converting the derived digital domain clock signal to an ultra-low phase-noise time domain voltage clock signal.

A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.

The present application provides a clock switching method, a clock switching apparatus, an electronic device, and a readable storage medium, the clock switching method includes: in a case where a first reference clock is determined to be in a locked state, determining an average control word according to a preset duration and an obtained real frequency tuning word; in a case where the first reference clock is determined to be in an invalid state, determining a compensation phase difference by using the average control word as a frequency control word of a digital phase locked loop; performing a phase compensation on a second reference clock according to the compensation phase difference to obtain an updated second reference clock; and switching the first reference clock to the updated second reference clock.

A method for correcting deterministic jitter in an all-digital phase-locked loop (ADPLL) is described. The method includes determining an offset to an input frequency of the ADPLL that causes an oscillator tuning word (OTW) provided to a digitally-controlled oscillator (DCO) quantizer to fall between two DCO codes. The method also includes applying the offset to the input frequency of the ADPLL to force the DCO quantizer to have gain.

A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.